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13 lines
315 B
Plaintext
13 lines
315 B
Plaintext
read_verilog latches.v
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proc
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flatten
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# Can't run any sort of equivalence check because latches are blown to LUTs
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#equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
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#design -load preopt
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synth_ice40
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cd top
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select -assert-count 4 t:SB_LUT4
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select -assert-none t:SB_LUT4 %% t:* %D
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