2019-08-08 03:31:34 -05:00
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`timescale 1ns / 1ps
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module testbench;
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parameter integer ACASCREG = 1;
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parameter integer ADREG = 1;
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parameter integer ALUMODEREG = 1;
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parameter integer AREG = 1;
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parameter AUTORESET_PATDET = "NO_RESET";
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parameter A_INPUT = "DIRECT";
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parameter integer BCASCREG = 1;
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parameter integer BREG = 1;
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parameter B_INPUT = "DIRECT";
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parameter integer CARRYINREG = 1;
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parameter integer CARRYINSELREG = 1;
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parameter integer CREG = 1;
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parameter integer DREG = 1;
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parameter integer INMODEREG = 1;
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parameter integer MREG = 1;
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parameter integer OPMODEREG = 1;
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parameter integer PREG = 1;
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parameter SEL_MASK = "MASK";
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parameter SEL_PATTERN = "PATTERN";
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parameter USE_DPORT = "FALSE";
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parameter USE_MULT = "MULTIPLY";
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parameter USE_PATTERN_DETECT = "NO_PATDET";
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parameter USE_SIMD = "ONE48";
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parameter [47:0] MASK = 48'h3FFFFFFFFFFF;
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parameter [47:0] PATTERN = 48'h000000000000;
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parameter [3:0] IS_ALUMODE_INVERTED = 4'b0;
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parameter [0:0] IS_CARRYIN_INVERTED = 1'b0;
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parameter [0:0] IS_CLK_INVERTED = 1'b0;
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parameter [4:0] IS_INMODE_INVERTED = 5'b0;
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parameter [6:0] IS_OPMODE_INVERTED = 7'b0;
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reg CLK;
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reg CEA1, CEA2, CEAD, CEALUMODE, CEB1, CEB2, CEC, CECARRYIN, CECTRL;
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reg CED, CEINMODE, CEM, CEP;
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2019-08-08 04:26:40 -05:00
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reg RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTCTRL, RSTD, RSTINMODE, RSTM, RSTP;
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2019-08-08 03:31:34 -05:00
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reg [29:0] A, ACIN;
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reg [17:0] B, BCIN;
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reg [47:0] C;
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reg [24:0] D;
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reg [47:0] PCIN;
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reg [3:0] ALUMODE;
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reg [2:0] CARRYINSEL;
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reg [4:0] INMODE;
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reg [6:0] OPMODE;
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reg CARRYCASCIN, CARRYIN, MULTSIGNIN;
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output [29:0] ACOUT, REF_ACOUT;
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output [17:0] BCOUT, REF_BCOUT;
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output CARRYCASCOUT, REF_CARRYCASCOUT;
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output [3:0] CARRYOUT, REF_CARRYOUT;
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output MULTSIGNOUT, REF_MULTSIGNOUT;
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output OVERFLOW, REF_OVERFLOW;
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output [47:0] P, REF_P;
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output PATTERNBDETECT, REF_PATTERNBDETECT;
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output PATTERNDETECT, REF_PATTERNDETECT;
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output [47:0] PCOUT, REF_PCOUT;
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output UNDERFLOW, REF_UNDERFLOW;
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integer errcount = 0;
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2019-08-08 04:26:40 -05:00
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reg ERROR_FLAG = 0;
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2019-08-08 03:31:34 -05:00
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task clkcycle;
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begin
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#5;
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CLK = ~CLK;
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#10;
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CLK = ~CLK;
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#2;
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2019-08-08 04:26:40 -05:00
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ERROR_FLAG = 0;
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2019-08-08 03:31:34 -05:00
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if (REF_P !== P) begin
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$display("ERROR at %1t: REF_P=%b UUT_P=%b DIFF=%b", $time, REF_P, P, REF_P ^ P);
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errcount = errcount + 1;
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2019-08-08 04:26:40 -05:00
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ERROR_FLAG = 1;
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2019-08-08 03:31:34 -05:00
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end
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if (REF_CARRYOUT !== CARRYOUT) begin
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$display("ERROR at %1t: REF_CARRYOUT=%b UUT_CARRYOUT=%b", $time, REF_CARRYOUT, CARRYOUT);
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errcount = errcount + 1;
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2019-08-08 04:26:40 -05:00
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ERROR_FLAG = 1;
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2019-08-08 03:31:34 -05:00
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end
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2019-09-18 12:45:04 -05:00
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if (REF_PATTERNDETECT !== PATTERNDETECT) begin
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$display("ERROR at %1t: REF_PATTERNDETECT=%b UUT_PATTERNDETECT=%b DIFF=%b REF_P=%b P=%b", $time, REF_PATTERNDETECT, PATTERNDETECT, REF_PATTERNDETECT ^ PATTERNDETECT, REF_P, P);
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errcount = errcount + 1;
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ERROR_FLAG = 1;
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end
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if (REF_PATTERNBDETECT !== PATTERNBDETECT) begin
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$display("ERROR at %1t: REF_PATTERNBDETECT=%b UUT_PATTERNBDETECT=%b DIFF=%b", $time, REF_PATTERNBDETECT, PATTERNBDETECT, REF_PATTERNBDETECT ^ PATTERNBDETECT);
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errcount = errcount + 1;
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ERROR_FLAG = 1;
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end
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if (REF_OVERFLOW !== OVERFLOW) begin
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$display("ERROR at %1t: REF_OVERFLOW=%b UUT_OVERFLOW=%b DIFF=%b", $time, REF_OVERFLOW, OVERFLOW, REF_OVERFLOW ^ OVERFLOW);
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errcount = errcount + 1;
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ERROR_FLAG = 1;
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end
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if (REF_UNDERFLOW !== UNDERFLOW) begin
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$display("ERROR at %1t: REF_UNDERFLOW=%b UUT_UNDERFLOW=%b DIFF=%b", $time, REF_UNDERFLOW, UNDERFLOW, REF_UNDERFLOW ^ UNDERFLOW);
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errcount = errcount + 1;
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ERROR_FLAG = 1;
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end
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2019-08-08 03:31:34 -05:00
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#3;
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end
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endtask
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reg config_valid = 0;
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task drc;
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2019-08-08 04:05:11 -05:00
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begin
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config_valid = 1;
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if (AREG != 2 && INMODE[0]) config_valid = 0;
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if (BREG != 2 && INMODE[4]) config_valid = 0;
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2019-08-08 05:18:37 -05:00
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2019-08-08 05:39:35 -05:00
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if (USE_SIMD != "ONE48" && OPMODE[3:0] == 4'b0101) config_valid = 0;
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2019-08-08 04:05:11 -05:00
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if (OPMODE[1:0] == 2'b10 && PREG != 1) config_valid = 0;
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if ((OPMODE[3:2] == 2'b01) ^ (OPMODE[1:0] == 2'b01) == 1'b1) config_valid = 0;
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if ((OPMODE[6:4] == 3'b010 || OPMODE[6:4] == 3'b110) && PREG != 1) config_valid = 0;
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2019-08-08 04:52:04 -05:00
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if ((OPMODE[6:4] == 3'b100) && (PREG != 1 || OPMODE[3:0] != 4'b1000 || ALUMODE[3:2] == 2'b01 || ALUMODE[3:2] == 2'b11)) config_valid = 0;
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2019-08-08 04:05:11 -05:00
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if ((CARRYINSEL == 3'b100 || CARRYINSEL == 3'b101 || CARRYINSEL == 3'b111) && (PREG != 1)) config_valid = 0;
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if (OPMODE[6:4] == 3'b111) config_valid = 0;
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if ((OPMODE[3:0] == 4'b0101) && CARRYINSEL == 3'b010) config_valid = 0;
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2019-08-08 05:18:37 -05:00
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if (CARRYINSEL == 3'b000 && OPMODE == 7'b1001000) config_valid = 0;
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if ((ALUMODE[3:2] == 2'b01 || ALUMODE[3:2] == 2'b11) && OPMODE[3:2] != 2'b00 && OPMODE[3:2] != 2'b10) config_valid = 0;
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2019-08-08 04:05:11 -05:00
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end
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2019-08-08 03:31:34 -05:00
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endtask
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initial begin
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$dumpfile("test_dsp_model.vcd");
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$dumpvars(0, testbench);
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#2;
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CLK = 1'b0;
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{CEA1, CEA2, CEAD, CEALUMODE, CEB1, CEB2, CEC, CECARRYIN, CECTRL} = 9'b111111111;
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{CED, CEINMODE, CEM, CEP} = 4'b1111;
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{A, B, C, D} = 0;
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{ACIN, BCIN, PCIN} = 0;
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{ALUMODE, CARRYINSEL, INMODE} = 0;
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{OPMODE, CARRYCASCIN, CARRYIN, MULTSIGNIN} = 0;
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2019-08-08 04:26:40 -05:00
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{RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTCTRL, RSTD, RSTINMODE, RSTM, RSTP} = ~0;
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2019-08-08 04:52:04 -05:00
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repeat (10) begin
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#10;
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CLK = 1'b1;
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#10;
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CLK = 1'b0;
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#10;
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CLK = 1'b1;
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#10;
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CLK = 1'b0;
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end
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2019-08-08 04:26:40 -05:00
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{RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTCTRL, RSTD, RSTINMODE, RSTM, RSTP} = 0;
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2019-08-08 03:31:34 -05:00
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2019-08-08 05:32:43 -05:00
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repeat (10000) begin
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2019-08-08 03:31:34 -05:00
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clkcycle;
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2019-08-08 04:05:11 -05:00
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config_valid = 0;
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while (!config_valid) begin
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2019-08-08 03:31:34 -05:00
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A = $urandom;
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ACIN = $urandom;
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B = $urandom;
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BCIN = $urandom;
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C = {$urandom, $urandom};
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D = $urandom;
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PCIN = {$urandom, $urandom};
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2019-08-08 05:32:43 -05:00
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{CEA1, CEA2, CEAD, CEALUMODE, CEB1, CEB2, CEC, CECARRYIN, CECTRL} = $urandom | $urandom | $urandom;
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{CED, CEINMODE, CEM, CEP} = $urandom | $urandom | $urandom | $urandom;
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// Otherwise we can accidentally create illegal configs
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CEINMODE = CECTRL;
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CEALUMODE = CECTRL;
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2019-08-08 04:26:40 -05:00
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{RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTCTRL, RSTD, RSTINMODE, RSTM, RSTP} = $urandom & $urandom & $urandom & $urandom & $urandom & $urandom;
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2019-08-08 05:18:37 -05:00
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{ALUMODE, INMODE} = $urandom;
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CARRYINSEL = $urandom & $urandom & $urandom;
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2019-08-08 04:05:11 -05:00
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OPMODE = $urandom;
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if ($urandom & 1'b1)
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OPMODE[3:0] = 4'b0101; // test multiply more than other modes
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2019-08-08 03:31:34 -05:00
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{CARRYCASCIN, CARRYIN, MULTSIGNIN} = $urandom;
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2019-08-08 05:18:37 -05:00
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// So few valid options in these modes, just force one valid option
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if (CARRYINSEL == 3'b001) OPMODE = 7'b1010101;
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if (CARRYINSEL == 3'b010) OPMODE = 7'b0001010;
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if (CARRYINSEL == 3'b011) OPMODE = 7'b0011011;
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if (CARRYINSEL == 3'b100) OPMODE = 7'b0110011;
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if (CARRYINSEL == 3'b101) OPMODE = 7'b0011010;
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if (CARRYINSEL == 3'b110) OPMODE = 7'b0010101;
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if (CARRYINSEL == 3'b111) OPMODE = 7'b0100011;
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2019-08-08 05:32:43 -05:00
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2019-08-08 03:31:34 -05:00
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drc;
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2019-08-08 04:05:11 -05:00
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end
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2019-08-08 03:31:34 -05:00
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end
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if (errcount == 0) begin
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$display("All tests passed.");
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$finish;
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end else begin
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$display("Caught %1d errors.", errcount);
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$stop;
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end
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end
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DSP48E1 #(
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.ACASCREG (ACASCREG),
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.ADREG (ADREG),
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.ALUMODEREG (ALUMODEREG),
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.AREG (AREG),
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.AUTORESET_PATDET (AUTORESET_PATDET),
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.A_INPUT (A_INPUT),
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.BCASCREG (BCASCREG),
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.BREG (BREG),
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.B_INPUT (B_INPUT),
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.CARRYINREG (CARRYINREG),
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.CARRYINSELREG (CARRYINSELREG),
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.CREG (CREG),
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.DREG (DREG),
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.INMODEREG (INMODEREG),
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.MREG (MREG),
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.OPMODEREG (OPMODEREG),
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.PREG (PREG),
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.SEL_MASK (SEL_MASK),
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.SEL_PATTERN (SEL_PATTERN),
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.USE_DPORT (USE_DPORT),
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.USE_MULT (USE_MULT),
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.USE_PATTERN_DETECT (USE_PATTERN_DETECT),
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.USE_SIMD (USE_SIMD),
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.MASK (MASK),
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.PATTERN (PATTERN),
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.IS_ALUMODE_INVERTED(IS_ALUMODE_INVERTED),
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.IS_CARRYIN_INVERTED(IS_CARRYIN_INVERTED),
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.IS_CLK_INVERTED (IS_CLK_INVERTED),
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.IS_INMODE_INVERTED (IS_INMODE_INVERTED),
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.IS_OPMODE_INVERTED (IS_OPMODE_INVERTED)
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) ref (
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.ACOUT (REF_ACOUT),
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.BCOUT (REF_BCOUT),
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.CARRYCASCOUT (REF_CARRYCASCOUT),
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.CARRYOUT (REF_CARRYOUT),
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.MULTSIGNOUT (REF_MULTSIGNOUT),
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.OVERFLOW (REF_OVERFLOW),
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.P (REF_P),
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.PATTERNBDETECT(REF_PATTERNBDETECT),
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.PATTERNDETECT (REF_PATTERNDETECT),
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.PCOUT (REF_PCOUT),
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.UNDERFLOW (REF_UNDERFLOW),
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.A (A),
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.ACIN (ACIN),
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.ALUMODE (ALUMODE),
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.B (B),
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.BCIN (BCIN),
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.C (C),
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.CARRYCASCIN (CARRYCASCIN),
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2019-08-08 04:05:11 -05:00
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.CARRYINSEL (CARRYINSEL),
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2019-08-08 03:31:34 -05:00
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.CEA1 (CEA1),
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.CEA2 (CEA2),
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.CEAD (CEAD),
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.CEALUMODE (CEALUMODE),
|
|
|
|
|
.CEB1 (CEB1),
|
|
|
|
|
.CEB2 (CEB2),
|
|
|
|
|
.CEC (CEC),
|
|
|
|
|
.CECARRYIN (CECARRYIN),
|
|
|
|
|
.CECTRL (CECTRL),
|
|
|
|
|
.CED (CED),
|
|
|
|
|
.CEINMODE (CEINMODE),
|
|
|
|
|
.CEM (CEM),
|
|
|
|
|
.CEP (CEP),
|
|
|
|
|
.CLK (CLK),
|
|
|
|
|
.D (D),
|
|
|
|
|
.INMODE (INMODE),
|
|
|
|
|
.MULTSIGNIN (MULTSIGNIN),
|
|
|
|
|
.OPMODE (OPMODE),
|
|
|
|
|
.PCIN (PCIN),
|
|
|
|
|
.RSTA (RSTA),
|
|
|
|
|
.RSTALLCARRYIN (RSTALLCARRYIN),
|
|
|
|
|
.RSTALUMODE (RSTALUMODE),
|
|
|
|
|
.RSTB (RSTB),
|
|
|
|
|
.RSTC (RSTC),
|
|
|
|
|
.RSTCTRL (RSTCTRL),
|
|
|
|
|
.RSTD (RSTD),
|
|
|
|
|
.RSTINMODE (RSTINMODE),
|
|
|
|
|
.RSTM (RSTM),
|
|
|
|
|
.RSTP (RSTP)
|
|
|
|
|
);
|
|
|
|
|
|
|
|
|
|
DSP48E1_UUT #(
|
|
|
|
|
.ACASCREG (ACASCREG),
|
|
|
|
|
.ADREG (ADREG),
|
|
|
|
|
.ALUMODEREG (ALUMODEREG),
|
|
|
|
|
.AREG (AREG),
|
|
|
|
|
.AUTORESET_PATDET (AUTORESET_PATDET),
|
|
|
|
|
.A_INPUT (A_INPUT),
|
|
|
|
|
.BCASCREG (BCASCREG),
|
|
|
|
|
.BREG (BREG),
|
|
|
|
|
.B_INPUT (B_INPUT),
|
|
|
|
|
.CARRYINREG (CARRYINREG),
|
|
|
|
|
.CARRYINSELREG (CARRYINSELREG),
|
|
|
|
|
.CREG (CREG),
|
|
|
|
|
.DREG (DREG),
|
|
|
|
|
.INMODEREG (INMODEREG),
|
|
|
|
|
.MREG (MREG),
|
|
|
|
|
.OPMODEREG (OPMODEREG),
|
|
|
|
|
.PREG (PREG),
|
|
|
|
|
.SEL_MASK (SEL_MASK),
|
|
|
|
|
.SEL_PATTERN (SEL_PATTERN),
|
|
|
|
|
.USE_DPORT (USE_DPORT),
|
|
|
|
|
.USE_MULT (USE_MULT),
|
|
|
|
|
.USE_PATTERN_DETECT (USE_PATTERN_DETECT),
|
|
|
|
|
.USE_SIMD (USE_SIMD),
|
|
|
|
|
.MASK (MASK),
|
|
|
|
|
.PATTERN (PATTERN),
|
|
|
|
|
.IS_ALUMODE_INVERTED(IS_ALUMODE_INVERTED),
|
|
|
|
|
.IS_CARRYIN_INVERTED(IS_CARRYIN_INVERTED),
|
|
|
|
|
.IS_CLK_INVERTED (IS_CLK_INVERTED),
|
|
|
|
|
.IS_INMODE_INVERTED (IS_INMODE_INVERTED),
|
|
|
|
|
.IS_OPMODE_INVERTED (IS_OPMODE_INVERTED)
|
|
|
|
|
) uut (
|
|
|
|
|
.ACOUT (ACOUT),
|
|
|
|
|
.BCOUT (BCOUT),
|
|
|
|
|
.CARRYCASCOUT (CARRYCASCOUT),
|
|
|
|
|
.CARRYOUT (CARRYOUT),
|
|
|
|
|
.MULTSIGNOUT (MULTSIGNOUT),
|
|
|
|
|
.OVERFLOW (OVERFLOW),
|
|
|
|
|
.P (P),
|
|
|
|
|
.PATTERNBDETECT(PATTERNBDETECT),
|
|
|
|
|
.PATTERNDETECT (PATTERNDETECT),
|
|
|
|
|
.PCOUT (PCOUT),
|
|
|
|
|
.UNDERFLOW (UNDERFLOW),
|
|
|
|
|
.A (A),
|
|
|
|
|
.ACIN (ACIN),
|
|
|
|
|
.ALUMODE (ALUMODE),
|
|
|
|
|
.B (B),
|
|
|
|
|
.BCIN (BCIN),
|
|
|
|
|
.C (C),
|
|
|
|
|
.CARRYCASCIN (CARRYCASCIN),
|
2019-08-08 04:05:11 -05:00
|
|
|
.CARRYINSEL (CARRYINSEL),
|
2019-08-08 03:31:34 -05:00
|
|
|
.CEA1 (CEA1),
|
|
|
|
|
.CEA2 (CEA2),
|
|
|
|
|
.CEAD (CEAD),
|
|
|
|
|
.CEALUMODE (CEALUMODE),
|
|
|
|
|
.CEB1 (CEB1),
|
|
|
|
|
.CEB2 (CEB2),
|
|
|
|
|
.CEC (CEC),
|
|
|
|
|
.CECARRYIN (CECARRYIN),
|
|
|
|
|
.CECTRL (CECTRL),
|
|
|
|
|
.CED (CED),
|
|
|
|
|
.CEINMODE (CEINMODE),
|
|
|
|
|
.CEM (CEM),
|
|
|
|
|
.CEP (CEP),
|
|
|
|
|
.CLK (CLK),
|
|
|
|
|
.D (D),
|
|
|
|
|
.INMODE (INMODE),
|
|
|
|
|
.MULTSIGNIN (MULTSIGNIN),
|
|
|
|
|
.OPMODE (OPMODE),
|
|
|
|
|
.PCIN (PCIN),
|
|
|
|
|
.RSTA (RSTA),
|
|
|
|
|
.RSTALLCARRYIN (RSTALLCARRYIN),
|
|
|
|
|
.RSTALUMODE (RSTALUMODE),
|
|
|
|
|
.RSTB (RSTB),
|
|
|
|
|
.RSTC (RSTC),
|
|
|
|
|
.RSTCTRL (RSTCTRL),
|
|
|
|
|
.RSTD (RSTD),
|
|
|
|
|
.RSTINMODE (RSTINMODE),
|
|
|
|
|
.RSTM (RSTM),
|
|
|
|
|
.RSTP (RSTP)
|
|
|
|
|
);
|
|
|
|
|
endmodule
|
2019-08-08 04:05:11 -05:00
|
|
|
|
|
|
|
|
module mult_noreg_nopreadd_nocasc;
|
|
|
|
|
testbench #(
|
|
|
|
|
.ACASCREG (0),
|
|
|
|
|
.ADREG (0),
|
|
|
|
|
.ALUMODEREG (0),
|
|
|
|
|
.AREG (0),
|
|
|
|
|
.AUTORESET_PATDET ("NO_RESET"),
|
|
|
|
|
.A_INPUT ("DIRECT"),
|
|
|
|
|
.BCASCREG (0),
|
|
|
|
|
.BREG (0),
|
|
|
|
|
.B_INPUT ("DIRECT"),
|
|
|
|
|
.CARRYINREG (0),
|
|
|
|
|
.CARRYINSELREG (0),
|
|
|
|
|
.CREG (0),
|
|
|
|
|
.DREG (0),
|
|
|
|
|
.INMODEREG (0),
|
|
|
|
|
.MREG (0),
|
|
|
|
|
.OPMODEREG (0),
|
|
|
|
|
.PREG (0),
|
|
|
|
|
.SEL_MASK ("MASK"),
|
|
|
|
|
.SEL_PATTERN ("PATTERN"),
|
|
|
|
|
.USE_DPORT ("FALSE"),
|
|
|
|
|
.USE_MULT ("DYNAMIC"),
|
|
|
|
|
.USE_PATTERN_DETECT ("NO_PATDET"),
|
|
|
|
|
.USE_SIMD ("ONE48"),
|
|
|
|
|
.MASK (48'h3FFFFFFFFFFF),
|
|
|
|
|
.PATTERN (48'h000000000000),
|
|
|
|
|
.IS_ALUMODE_INVERTED(4'b0),
|
|
|
|
|
.IS_CARRYIN_INVERTED(1'b0),
|
|
|
|
|
.IS_CLK_INVERTED (1'b0),
|
|
|
|
|
.IS_INMODE_INVERTED (5'b0),
|
|
|
|
|
.IS_OPMODE_INVERTED (7'b0)
|
|
|
|
|
) testbench ();
|
2019-08-08 04:52:04 -05:00
|
|
|
endmodule
|
|
|
|
|
|
|
|
|
|
module mult_allreg_nopreadd_nocasc;
|
|
|
|
|
testbench #(
|
|
|
|
|
.ACASCREG (1),
|
|
|
|
|
.ADREG (1),
|
|
|
|
|
.ALUMODEREG (1),
|
|
|
|
|
.AREG (2),
|
|
|
|
|
.AUTORESET_PATDET ("NO_RESET"),
|
|
|
|
|
.A_INPUT ("DIRECT"),
|
|
|
|
|
.BCASCREG (1),
|
|
|
|
|
.BREG (2),
|
|
|
|
|
.B_INPUT ("DIRECT"),
|
|
|
|
|
.CARRYINREG (1),
|
|
|
|
|
.CARRYINSELREG (1),
|
|
|
|
|
.CREG (1),
|
|
|
|
|
.DREG (1),
|
|
|
|
|
.INMODEREG (1),
|
|
|
|
|
.MREG (1),
|
|
|
|
|
.OPMODEREG (1),
|
|
|
|
|
.PREG (1),
|
|
|
|
|
.SEL_MASK ("MASK"),
|
|
|
|
|
.SEL_PATTERN ("PATTERN"),
|
|
|
|
|
.USE_DPORT ("FALSE"),
|
|
|
|
|
.USE_MULT ("DYNAMIC"),
|
|
|
|
|
.USE_PATTERN_DETECT ("NO_PATDET"),
|
|
|
|
|
.USE_SIMD ("ONE48"),
|
|
|
|
|
.MASK (48'h3FFFFFFFFFFF),
|
|
|
|
|
.PATTERN (48'h000000000000),
|
|
|
|
|
.IS_ALUMODE_INVERTED(4'b0),
|
|
|
|
|
.IS_CARRYIN_INVERTED(1'b0),
|
|
|
|
|
.IS_CLK_INVERTED (1'b0),
|
|
|
|
|
.IS_INMODE_INVERTED (5'b0),
|
|
|
|
|
.IS_OPMODE_INVERTED (7'b0)
|
|
|
|
|
) testbench ();
|
2019-08-08 05:18:37 -05:00
|
|
|
endmodule
|
|
|
|
|
|
|
|
|
|
module mult_noreg_preadd_nocasc;
|
|
|
|
|
testbench #(
|
|
|
|
|
.ACASCREG (0),
|
|
|
|
|
.ADREG (0),
|
|
|
|
|
.ALUMODEREG (0),
|
|
|
|
|
.AREG (0),
|
|
|
|
|
.AUTORESET_PATDET ("NO_RESET"),
|
|
|
|
|
.A_INPUT ("DIRECT"),
|
|
|
|
|
.BCASCREG (0),
|
|
|
|
|
.BREG (0),
|
|
|
|
|
.B_INPUT ("DIRECT"),
|
|
|
|
|
.CARRYINREG (0),
|
|
|
|
|
.CARRYINSELREG (0),
|
|
|
|
|
.CREG (0),
|
|
|
|
|
.DREG (0),
|
|
|
|
|
.INMODEREG (0),
|
|
|
|
|
.MREG (0),
|
|
|
|
|
.OPMODEREG (0),
|
|
|
|
|
.PREG (0),
|
|
|
|
|
.SEL_MASK ("MASK"),
|
|
|
|
|
.SEL_PATTERN ("PATTERN"),
|
|
|
|
|
.USE_DPORT ("TRUE"),
|
|
|
|
|
.USE_MULT ("DYNAMIC"),
|
|
|
|
|
.USE_PATTERN_DETECT ("NO_PATDET"),
|
|
|
|
|
.USE_SIMD ("ONE48"),
|
|
|
|
|
.MASK (48'h3FFFFFFFFFFF),
|
|
|
|
|
.PATTERN (48'h000000000000),
|
|
|
|
|
.IS_ALUMODE_INVERTED(4'b0),
|
|
|
|
|
.IS_CARRYIN_INVERTED(1'b0),
|
|
|
|
|
.IS_CLK_INVERTED (1'b0),
|
|
|
|
|
.IS_INMODE_INVERTED (5'b0),
|
|
|
|
|
.IS_OPMODE_INVERTED (7'b0)
|
|
|
|
|
) testbench ();
|
|
|
|
|
endmodule
|
|
|
|
|
|
|
|
|
|
module mult_allreg_preadd_nocasc;
|
|
|
|
|
testbench #(
|
|
|
|
|
.ACASCREG (1),
|
|
|
|
|
.ADREG (1),
|
|
|
|
|
.ALUMODEREG (1),
|
|
|
|
|
.AREG (2),
|
|
|
|
|
.AUTORESET_PATDET ("NO_RESET"),
|
|
|
|
|
.A_INPUT ("DIRECT"),
|
|
|
|
|
.BCASCREG (1),
|
|
|
|
|
.BREG (2),
|
|
|
|
|
.B_INPUT ("DIRECT"),
|
|
|
|
|
.CARRYINREG (1),
|
|
|
|
|
.CARRYINSELREG (1),
|
|
|
|
|
.CREG (1),
|
|
|
|
|
.DREG (1),
|
|
|
|
|
.INMODEREG (1),
|
|
|
|
|
.MREG (1),
|
|
|
|
|
.OPMODEREG (1),
|
|
|
|
|
.PREG (1),
|
|
|
|
|
.SEL_MASK ("MASK"),
|
|
|
|
|
.SEL_PATTERN ("PATTERN"),
|
|
|
|
|
.USE_DPORT ("TRUE"),
|
|
|
|
|
.USE_MULT ("DYNAMIC"),
|
|
|
|
|
.USE_PATTERN_DETECT ("NO_PATDET"),
|
|
|
|
|
.USE_SIMD ("ONE48"),
|
|
|
|
|
.MASK (48'h3FFFFFFFFFFF),
|
|
|
|
|
.PATTERN (48'h000000000000),
|
|
|
|
|
.IS_ALUMODE_INVERTED(4'b0),
|
|
|
|
|
.IS_CARRYIN_INVERTED(1'b0),
|
|
|
|
|
.IS_CLK_INVERTED (1'b0),
|
|
|
|
|
.IS_INMODE_INVERTED (5'b0),
|
|
|
|
|
.IS_OPMODE_INVERTED (7'b0)
|
|
|
|
|
) testbench ();
|
2019-08-08 05:39:35 -05:00
|
|
|
endmodule
|
|
|
|
|
|
|
|
|
|
module mult_inreg_preadd_nocasc;
|
|
|
|
|
testbench #(
|
|
|
|
|
.ACASCREG (1),
|
|
|
|
|
.ADREG (0),
|
|
|
|
|
.ALUMODEREG (0),
|
|
|
|
|
.AREG (1),
|
|
|
|
|
.AUTORESET_PATDET ("NO_RESET"),
|
|
|
|
|
.A_INPUT ("DIRECT"),
|
|
|
|
|
.BCASCREG (1),
|
|
|
|
|
.BREG (1),
|
|
|
|
|
.B_INPUT ("DIRECT"),
|
|
|
|
|
.CARRYINREG (0),
|
|
|
|
|
.CARRYINSELREG (0),
|
|
|
|
|
.CREG (1),
|
|
|
|
|
.DREG (1),
|
|
|
|
|
.INMODEREG (0),
|
|
|
|
|
.MREG (0),
|
|
|
|
|
.OPMODEREG (0),
|
|
|
|
|
.PREG (0),
|
|
|
|
|
.SEL_MASK ("MASK"),
|
|
|
|
|
.SEL_PATTERN ("PATTERN"),
|
|
|
|
|
.USE_DPORT ("TRUE"),
|
|
|
|
|
.USE_MULT ("DYNAMIC"),
|
|
|
|
|
.USE_PATTERN_DETECT ("NO_PATDET"),
|
|
|
|
|
.USE_SIMD ("ONE48"),
|
|
|
|
|
.MASK (48'h3FFFFFFFFFFF),
|
|
|
|
|
.PATTERN (48'h000000000000),
|
|
|
|
|
.IS_ALUMODE_INVERTED(4'b0),
|
|
|
|
|
.IS_CARRYIN_INVERTED(1'b0),
|
|
|
|
|
.IS_CLK_INVERTED (1'b0),
|
|
|
|
|
.IS_INMODE_INVERTED (5'b0),
|
|
|
|
|
.IS_OPMODE_INVERTED (7'b0)
|
|
|
|
|
) testbench ();
|
|
|
|
|
endmodule
|
|
|
|
|
|
|
|
|
|
module simd12_preadd_noreg_nocasc;
|
|
|
|
|
testbench #(
|
|
|
|
|
.ACASCREG (0),
|
|
|
|
|
.ADREG (0),
|
|
|
|
|
.ALUMODEREG (0),
|
|
|
|
|
.AREG (0),
|
|
|
|
|
.AUTORESET_PATDET ("NO_RESET"),
|
|
|
|
|
.A_INPUT ("DIRECT"),
|
|
|
|
|
.BCASCREG (0),
|
|
|
|
|
.BREG (0),
|
|
|
|
|
.B_INPUT ("DIRECT"),
|
|
|
|
|
.CARRYINREG (0),
|
|
|
|
|
.CARRYINSELREG (0),
|
|
|
|
|
.CREG (0),
|
|
|
|
|
.DREG (0),
|
|
|
|
|
.INMODEREG (0),
|
|
|
|
|
.MREG (0),
|
|
|
|
|
.OPMODEREG (0),
|
|
|
|
|
.PREG (0),
|
|
|
|
|
.SEL_MASK ("MASK"),
|
|
|
|
|
.SEL_PATTERN ("PATTERN"),
|
|
|
|
|
.USE_DPORT ("TRUE"),
|
|
|
|
|
.USE_MULT ("DYNAMIC"),
|
|
|
|
|
.USE_PATTERN_DETECT ("NO_PATDET"),
|
|
|
|
|
.USE_SIMD ("FOUR12"),
|
|
|
|
|
.MASK (48'h3FFFFFFFFFFF),
|
|
|
|
|
.PATTERN (48'h000000000000),
|
|
|
|
|
.IS_ALUMODE_INVERTED(4'b0),
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.IS_CARRYIN_INVERTED(1'b0),
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.IS_CLK_INVERTED (1'b0),
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.IS_INMODE_INVERTED (5'b0),
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.IS_OPMODE_INVERTED (7'b0)
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) testbench ();
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endmodule
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module simd24_preadd_noreg_nocasc;
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testbench #(
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.ACASCREG (0),
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.ADREG (0),
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.ALUMODEREG (0),
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.AREG (0),
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.AUTORESET_PATDET ("NO_RESET"),
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.A_INPUT ("DIRECT"),
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.BCASCREG (0),
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.BREG (0),
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.B_INPUT ("DIRECT"),
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.CARRYINREG (0),
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.CARRYINSELREG (0),
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.CREG (0),
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.DREG (0),
|
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.INMODEREG (0),
|
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.MREG (0),
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.OPMODEREG (0),
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.PREG (0),
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.SEL_MASK ("MASK"),
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.SEL_PATTERN ("PATTERN"),
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.USE_DPORT ("TRUE"),
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.USE_MULT ("DYNAMIC"),
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.USE_PATTERN_DETECT ("NO_PATDET"),
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.USE_SIMD ("TWO24"),
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.MASK (48'h3FFFFFFFFFFF),
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.PATTERN (48'h000000000000),
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.IS_ALUMODE_INVERTED(4'b0),
|
|
|
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|
.IS_CARRYIN_INVERTED(1'b0),
|
|
|
|
|
.IS_CLK_INVERTED (1'b0),
|
|
|
|
|
.IS_INMODE_INVERTED (5'b0),
|
|
|
|
|
.IS_OPMODE_INVERTED (7'b0)
|
|
|
|
|
) testbench ();
|
2019-09-18 12:45:04 -05:00
|
|
|
endmodule
|
|
|
|
|
|
|
|
|
|
module macc_overflow_underflow;
|
|
|
|
|
testbench #(
|
|
|
|
|
.ACASCREG (0),
|
|
|
|
|
.ADREG (0),
|
|
|
|
|
.ALUMODEREG (0),
|
|
|
|
|
.AREG (0),
|
|
|
|
|
.AUTORESET_PATDET ("NO_RESET"),
|
|
|
|
|
.A_INPUT ("DIRECT"),
|
|
|
|
|
.BCASCREG (0),
|
|
|
|
|
.BREG (0),
|
|
|
|
|
.B_INPUT ("DIRECT"),
|
|
|
|
|
.CARRYINREG (0),
|
|
|
|
|
.CARRYINSELREG (0),
|
|
|
|
|
.CREG (0),
|
|
|
|
|
.DREG (0),
|
|
|
|
|
.INMODEREG (0),
|
|
|
|
|
.MREG (0),
|
|
|
|
|
.OPMODEREG (0),
|
|
|
|
|
.PREG (1),
|
|
|
|
|
.SEL_MASK ("MASK"),
|
|
|
|
|
.SEL_PATTERN ("PATTERN"),
|
|
|
|
|
.USE_DPORT ("FALSE"),
|
|
|
|
|
.USE_MULT ("DYNAMIC"),
|
|
|
|
|
.USE_PATTERN_DETECT ("PATDET"),
|
|
|
|
|
.USE_SIMD ("ONE48"),
|
|
|
|
|
.MASK (48'h1FFFFFFFFFFF),
|
|
|
|
|
.PATTERN (48'h000000000000),
|
|
|
|
|
.IS_ALUMODE_INVERTED(4'b0),
|
|
|
|
|
.IS_CARRYIN_INVERTED(1'b0),
|
|
|
|
|
.IS_CLK_INVERTED (1'b0),
|
|
|
|
|
.IS_INMODE_INVERTED (5'b0),
|
|
|
|
|
.IS_OPMODE_INVERTED (7'b0)
|
|
|
|
|
) testbench ();
|
|
|
|
|
endmodule
|
