mirror of https://github.com/YosysHQ/yosys.git
52 lines
882 B
Verilog
52 lines
882 B
Verilog
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module \$__MUL27X18 (input [26:0] A, input [17:0] B, output [44:0] Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 0;
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parameter B_WIDTH = 0;
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parameter Y_WIDTH = 0;
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wire [47:0] P_48;
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DSP48E2 #(
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// Disable all registers
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.ACASCREG(0),
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.ADREG(0),
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.A_INPUT("DIRECT"),
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.ALUMODEREG(0),
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.AREG(0),
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.BCASCREG(0),
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.B_INPUT("DIRECT"),
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.BREG(0),
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.CARRYINREG(0),
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.CARRYINSELREG(0),
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.CREG(0),
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.DREG(0),
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.INMODEREG(0),
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.MREG(0),
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.OPMODEREG(0),
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.PREG(0),
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.USE_MULT("MULTIPLY"),
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.USE_SIMD("ONE48"),
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.AMULTSEL("A"),
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.BMULTSEL("B")
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) _TECHMAP_REPLACE_ (
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//Data path
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.A({{3{A[26]}}, A}),
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.B(B),
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.C(48'b0),
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.D(27'b0),
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.P(P_48),
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.INMODE(5'b00000),
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.ALUMODE(4'b0000),
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.OPMODE(9'b00000101),
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.CARRYINSEL(3'b000),
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.ACIN(30'b0),
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.BCIN(18'b0),
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.PCIN(48'b0),
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.CARRYIN(1'b0)
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);
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assign Y = P_48;
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endmodule
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