yosys/techlibs/xilinx/drams.txt


bram $__XILINX_RAM64X1D
  init 1
  abits 6
  dbits 1
  groups 2
  ports  1 1
  wrmode 0 1
  enable 0 1
  transp 0 0
  clocks 0 1
  clkpol 0 2
endbram

bram $__XILINX_RAM128X1D
  init 1
  abits 7
  dbits 1
  groups 2
  ports  1 1
  wrmode 0 1
  enable 0 1
  transp 0 0
  clocks 0 1
  clkpol 0 2
endbram

match $__XILINX_RAM64X1D
  min bits 5
  min wports 1
  make_outreg
  or_next_if_better
endmatch

match $__XILINX_RAM128X1D
  min bits 9
  min wports 1
  make_outreg
endmatch
Towards DRAM support in Xilinx flow 2015-04-09 01:17:14 -05:00
Xilinx DRAMS: RAM64X1D, RAM128X1D 2015-04-09 06:37:07 -05:00			`bram $__XILINX_RAM64X1D`
Towards DRAM support in Xilinx flow 2015-04-09 01:17:14 -05:00			`init 1`
Xilinx DRAMS: RAM64X1D, RAM128X1D 2015-04-09 06:37:07 -05:00			`abits 6`
Towards DRAM support in Xilinx flow 2015-04-09 01:17:14 -05:00			`dbits 1`
			`groups 2`
			`ports 1 1`
			`wrmode 0 1`
			`enable 0 1`
			`transp 0 0`
			`clocks 0 1`
			`clkpol 0 2`
			`endbram`

Xilinx DRAMS: RAM64X1D, RAM128X1D 2015-04-09 06:37:07 -05:00			`bram $__XILINX_RAM128X1D`
			`init 1`
			`abits 7`
			`dbits 1`
			`groups 2`
			`ports 1 1`
			`wrmode 0 1`
			`enable 0 1`
			`transp 0 0`
			`clocks 0 1`
			`clkpol 0 2`
			`endbram`

			`match $__XILINX_RAM64X1D`
Add "min bits" and "min wports" to xilinx dram rules 2019-05-23 13:32:28 -05:00			`min bits 5`
			`min wports 1`
Added memory_bram "make_outreg" feature 2015-04-09 09:08:54 -05:00			`make_outreg`
Xilinx DRAMS: RAM64X1D, RAM128X1D 2015-04-09 06:37:07 -05:00			`or_next_if_better`
			`endmatch`

			`match $__XILINX_RAM128X1D`
Add "min bits" and "min wports" to xilinx dram rules 2019-05-23 13:32:28 -05:00			`min bits 9`
			`min wports 1`
Added memory_bram "make_outreg" feature 2015-04-09 09:08:54 -05:00			`make_outreg`
Towards DRAM support in Xilinx flow 2015-04-09 01:17:14 -05:00			`endmatch`