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yosys/techlibs/xilinx/drams.txt

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Towards DRAM support in Xilinx flow
2015-04-09 01:17:14 -05:00
Xilinx DRAMS: RAM64X1D, RAM128X1D
2015-04-09 06:37:07 -05:00
bram $__XILINX_RAM64X1D
Towards DRAM support in Xilinx flow
2015-04-09 01:17:14 -05:00
init 1
Xilinx DRAMS: RAM64X1D, RAM128X1D
2015-04-09 06:37:07 -05:00
abits 6
Towards DRAM support in Xilinx flow
2015-04-09 01:17:14 -05:00
dbits 1
groups 2
ports 1 1
wrmode 0 1
enable 0 1
transp 0 0
clocks 0 1
clkpol 0 2
endbram
Xilinx DRAMS: RAM64X1D, RAM128X1D
2015-04-09 06:37:07 -05:00
bram $__XILINX_RAM128X1D
init 1
abits 7
dbits 1
groups 2
ports 1 1
wrmode 0 1
enable 0 1
transp 0 0
clocks 0 1
clkpol 0 2
endbram
match $__XILINX_RAM64X1D
or_next_if_better
endmatch
match $__XILINX_RAM128X1D
Towards DRAM support in Xilinx flow
2015-04-09 01:17:14 -05:00
endmatch