yosys

mirror of https://github.com/YosysHQ/yosys.git

Author	SHA1	Message	Date
Eddie Hung	99a3fee8f4	Add "min bits" and "min wports" to xilinx dram rules	2019-05-23 11:32:28 -07:00
Clifford Wolf	7319951145	Added memory_bram "make_outreg" feature	2015-04-09 16:08:54 +02:00
Clifford Wolf	229825e1b8	Xilinx DRAMS: RAM64X1D, RAM128X1D	2015-04-09 13:37:07 +02:00
Clifford Wolf	b00cad81d7	Towards DRAM support in Xilinx flow	2015-04-09 08:17:14 +02:00