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yosys/techlibs/xilinx/cells.box

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Add delays to cells.box
2019-04-09 16:32:10 -05:00
# Max delays from https://pastebin.com/v2hrcksd
# from https://github.com/SymbiFlow/prjxray/pull/706#issuecomment-479380321
Add techlibs/xilinx/cells.box
2019-04-09 12:58:58 -05:00
Add delays to cells.box
2019-04-09 16:32:10 -05:00
# F7BMUX slower than F7AMUX
# Inputs: 0 1 S0
# Outputs: OUT
F7BMUX 1 0 3 1
217 223 296
# Inputs: 0 1 S0
# Outputs: OUT
MUXF8 2 0 3 1
104 94 273