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yosys/tests/arch/common/mul.v

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Add tests for ECP5 architecture
2019-09-03 03:53:37 -05:00
module top
intel_alm: Add multiply signedness to cells Quartus assumes unsigned multiplication by default, breaking signed multiplies, so add an input signedness parameter to the MISTRAL_MUL* cells to propagate to Quartus' <family>_mac cells.
2020-08-26 12:44:48 -05:00
#(parameter X_WIDTH=6, Y_WIDTH=6, A_WIDTH=12)
Add tests for ECP5 architecture
2019-09-03 03:53:37 -05:00
(
intel_alm: Add multiply signedness to cells Quartus assumes unsigned multiplication by default, breaking signed multiplies, so add an input signedness parameter to the MISTRAL_MUL* cells to propagate to Quartus' <family>_mac cells.
2020-08-26 12:44:48 -05:00
input [X_WIDTH-1:0] x,
input [Y_WIDTH-1:0] y,
Add tests for ECP5 architecture
2019-09-03 03:53:37 -05:00
intel_alm: Add multiply signedness to cells Quartus assumes unsigned multiplication by default, breaking signed multiplies, so add an input signedness parameter to the MISTRAL_MUL* cells to propagate to Quartus' <family>_mac cells.
2020-08-26 12:44:48 -05:00
output [A_WIDTH-1:0] A,
Unify verilog style
2019-10-18 05:50:24 -05:00
);
assign A = x * y;
Add tests for ECP5 architecture
2019-09-03 03:53:37 -05:00
endmodule