2019-10-18 05:19:59 -05:00
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read_verilog ../common/mul.v
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2019-09-10 00:08:03 -05:00
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hierarchy -top top
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2019-10-18 01:06:57 -05:00
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proc
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2019-12-28 09:22:24 -06:00
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equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
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2019-09-10 00:08:03 -05:00
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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2019-09-30 16:38:06 -05:00
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select -assert-count 1 t:DSP48E1
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2019-12-28 09:12:45 -06:00
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select -assert-none t:DSP48E1 %% t:* %D
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2019-12-22 13:43:39 -06:00
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design -reset
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read_verilog ../common/mul.v
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hierarchy -top top
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proc
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2019-12-28 09:43:19 -06:00
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equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s -noiopad # equivalency check
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2019-12-22 13:43:39 -06:00
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:DSP48A1
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select -assert-none t:DSP48A1 %% t:* %D
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