yosys/techlibs/greenpak4/cells_sim.v

mirror of https://github.com/YosysHQ/yosys.git
`timescale 1ns/1ps

`include "cells_sim_ams.v"
`include "cells_sim_digital.v"
`include "cells_sim_wip.v"
Fixed extra semicolon 2016-05-07 23:14:18 -05:00			`timescale 1ns/1ps
Added simulation timescale declaration 2016-05-07 23:13:47 -05:00
Refactored GreenPAK4 cells_sim into cells_sim_ams and cells_sim_digital 2017-08-05 18:33:24 -05:00			`include "cells_sim_ams.v"
			`include "cells_sim_digital.v"
Refactoring: moved modules still in cells_sim to cells_sim_wip 2017-08-29 15:23:23 -05:00			`include "cells_sim_wip.v"