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yosys/tests/arch/intel_alm/blockram.ys

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intel_alm: direct M10K instantiation This reverts commit a3a90f6377f251d3b6c5898eb1543f8832493bb8.
2020-07-26 13:28:10 -05:00
read_verilog ../common/blockram.v
chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 10 sync_ram_sdp
Fix for sync_ram_sdp not being final module Explicitly declare -top in synth_intel_alm.
2022-07-10 19:31:38 -05:00
synth_intel_alm -top sync_ram_sdp -family cyclonev -noiopad -noclkbuf
intel_alm: direct M10K instantiation This reverts commit a3a90f6377f251d3b6c5898eb1543f8832493bb8.
2020-07-26 13:28:10 -05:00
cd sync_ram_sdp
intel_alm: M10K write-enable is negative-true
2022-03-09 10:40:32 -06:00
select -assert-count 1 t:MISTRAL_NOT
intel_alm: direct M10K instantiation This reverts commit a3a90f6377f251d3b6c5898eb1543f8832493bb8.
2020-07-26 13:28:10 -05:00
select -assert-count 1 t:MISTRAL_M10K
intel_alm: M10K write-enable is negative-true
2022-03-09 10:40:32 -06:00
select -assert-none t:MISTRAL_NOT t:MISTRAL_M10K %% t:* %D