mirror of https://github.com/YosysHQ/yosys.git
Fix for sync_ram_sdp not being final module
Explicitly declare -top in synth_intel_alm.
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read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 10 sync_ram_sdp
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synth_intel_alm -family cyclonev -noiopad -noclkbuf
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synth_intel_alm -top sync_ram_sdp -family cyclonev -noiopad -noclkbuf
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cd sync_ram_sdp
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select -assert-count 1 t:MISTRAL_NOT
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select -assert-count 1 t:MISTRAL_M10K
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