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yosys/tests/opt/opt_lut.ys

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opt_lut: new pass, to combine LUTs for tighter packing.
2018-12-04 18:23:22 -06:00
read_verilog opt_lut.v
Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder" This reverts commit c851dc13108021834533094a8a3236da6d9e0161, reversing changes made to f54bf1631ff37a83733c162e6ebd188c1d5ea18f.
2019-08-12 14:06:45 -05:00
equiv_opt -map +/ice40/cells_sim.v -assert synth_ice40