yosys/tests/opt/opt_lut.ys

mirror of https://github.com/YosysHQ/yosys.git
read_verilog opt_lut.v
synth_ice40
ice40_unlut
equiv_opt -map +/ice40/cells_sim.v -assert opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3
opt_lut: new pass, to combine LUTs for tighter packing. 2018-12-04 18:23:22 -06:00			`read_verilog opt_lut.v`
Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER" 2019-08-10 11:14:48 -05:00			`synth_ice40`
			`ice40_unlut`
			`equiv_opt -map +/ice40/cells_sim.v -assert opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3`