2019-08-12 14:06:45 -05:00
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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2021-06-07 17:39:36 -05:00
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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2019-08-12 14:06:45 -05:00
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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#include "passes/pmgen/ice40_wrapcarry_pm.h"
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void create_ice40_wrapcarry(ice40_wrapcarry_pm &pm)
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{
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auto &st = pm.st_ice40_wrapcarry;
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#if 0
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log("\n");
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log("carry: %s\n", log_id(st.carry, "--"));
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log("lut: %s\n", log_id(st.lut, "--"));
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#endif
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log(" replacing SB_LUT + SB_CARRY with $__ICE40_CARRY_WRAPPER cell.\n");
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2020-04-02 11:51:32 -05:00
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Cell *cell = pm.module->addCell(NEW_ID, ID($__ICE40_CARRY_WRAPPER));
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pm.module->swap_names(cell, st.carry);
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2020-04-02 11:51:32 -05:00
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cell->setPort(ID::A, st.carry->getPort(ID(I0)));
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cell->setPort(ID::B, st.carry->getPort(ID(I1)));
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auto CI = st.carry->getPort(ID::CI);
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cell->setPort(ID::CI, CI);
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cell->setPort(ID::CO, st.carry->getPort(ID::CO));
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2019-08-12 14:06:45 -05:00
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2020-04-02 11:51:32 -05:00
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cell->setPort(ID(I0), st.lut->getPort(ID(I0)));
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auto I3 = st.lut->getPort(ID(I3));
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2020-01-24 13:59:48 -06:00
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if (pm.sigmap(CI) == pm.sigmap(I3)) {
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2020-04-02 11:51:32 -05:00
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cell->setParam(ID(I3_IS_CI), State::S1);
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I3 = State::Sx;
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}
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else
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cell->setParam(ID(I3_IS_CI), State::S0);
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cell->setPort(ID(I3), I3);
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cell->setPort(ID::O, st.lut->getPort(ID::O));
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cell->setParam(ID::LUT, st.lut->getParam(ID(LUT_INIT)));
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2019-12-09 13:48:28 -06:00
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for (const auto &a : st.carry->attributes)
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cell->attributes[stringf("\\SB_CARRY.%s", a.first.c_str())] = a.second;
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for (const auto &a : st.lut->attributes)
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cell->attributes[stringf("\\SB_LUT4.%s", a.first.c_str())] = a.second;
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cell->attributes[ID(SB_LUT4.name)] = Const(st.lut->name.str());
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if (st.carry->get_bool_attribute(ID::keep) || st.lut->get_bool_attribute(ID::keep))
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cell->attributes[ID::keep] = true;
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2019-12-03 16:48:11 -06:00
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2019-08-12 14:06:45 -05:00
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pm.autoremove(st.carry);
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pm.autoremove(st.lut);
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}
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struct Ice40WrapCarryPass : public Pass {
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Ice40WrapCarryPass() : Pass("ice40_wrapcarry", "iCE40: wrap carries") { }
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2020-06-18 18:34:52 -05:00
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" ice40_wrapcarry [selection]\n");
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log("\n");
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log("Wrap manually instantiated SB_CARRY cells, along with their associated SB_LUT4s,\n");
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log("into an internal $__ICE40_CARRY_WRAPPER cell for preservation across technology\n");
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log("mapping.\n");
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log("\n");
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log("Attributes on both cells will have their names prefixed with 'SB_CARRY.' or\n");
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log("'SB_LUT4.' and attached to the wrapping cell.\n");
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log("A (* keep *) attribute on either cell will be logically OR-ed together.\n");
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log("\n");
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log(" -unwrap\n");
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log(" unwrap $__ICE40_CARRY_WRAPPER cells back into SB_CARRYs and SB_LUT4s,\n");
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log(" including restoring their attributes.\n");
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2019-12-06 19:27:47 -06:00
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log("\n");
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2019-08-12 14:06:45 -05:00
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}
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2020-06-18 18:34:52 -05:00
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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2019-12-09 13:48:28 -06:00
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bool unwrap = false;
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2019-08-12 14:06:45 -05:00
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log_header(design, "Executing ICE40_WRAPCARRY pass (wrap carries).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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2019-12-09 13:48:28 -06:00
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if (args[argidx] == "-unwrap") {
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unwrap = true;
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continue;
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}
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2019-08-12 14:06:45 -05:00
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break;
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}
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extra_args(args, argidx, design);
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2019-12-09 13:48:28 -06:00
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for (auto module : design->selected_modules()) {
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if (!unwrap)
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ice40_wrapcarry_pm(module, module->selected_cells()).run_ice40_wrapcarry(create_ice40_wrapcarry);
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else {
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for (auto cell : module->selected_cells()) {
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if (cell->type != ID($__ICE40_CARRY_WRAPPER))
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continue;
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auto carry = module->addCell(NEW_ID, ID(SB_CARRY));
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2020-04-02 11:51:32 -05:00
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carry->setPort(ID(I0), cell->getPort(ID::A));
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carry->setPort(ID(I1), cell->getPort(ID::B));
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carry->setPort(ID::CI, cell->getPort(ID::CI));
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carry->setPort(ID::CO, cell->getPort(ID::CO));
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2019-12-09 13:48:28 -06:00
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module->swap_names(carry, cell);
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2019-12-09 14:45:22 -06:00
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auto lut_name = cell->attributes.at(ID(SB_LUT4.name), Const(NEW_ID.str())).decode_string();
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2019-12-09 15:27:09 -06:00
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auto lut = module->addCell(lut_name, ID($lut));
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2020-04-02 11:51:32 -05:00
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lut->setParam(ID::WIDTH, 4);
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lut->setParam(ID::LUT, cell->getParam(ID::LUT));
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auto I3 = cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID::CI : ID(I3));
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lut->setPort(ID::A, { I3, cell->getPort(ID::B), cell->getPort(ID::A), cell->getPort(ID(I0)) });
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lut->setPort(ID::Y, cell->getPort(ID::O));
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2019-12-09 13:48:28 -06:00
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2019-12-09 16:28:54 -06:00
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Const src;
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for (const auto &a : cell->attributes)
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if (a.first.begins_with("\\SB_CARRY.\\"))
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carry->attributes[a.first.c_str() + strlen("\\SB_CARRY.")] = a.second;
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else if (a.first.begins_with("\\SB_LUT4.\\"))
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lut->attributes[a.first.c_str() + strlen("\\SB_LUT4.")] = a.second;
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else if (a.first == ID::src)
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src = a.second;
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else if (a.first.in(ID(SB_LUT4.name), ID::keep, ID::module_not_derived))
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continue;
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else
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log_abort();
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2019-12-09 16:28:54 -06:00
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if (!src.empty()) {
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2020-04-02 11:51:32 -05:00
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carry->attributes.insert(std::make_pair(ID::src, src));
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lut->attributes.insert(std::make_pair(ID::src, src));
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2019-12-09 16:28:54 -06:00
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}
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2019-12-09 13:48:28 -06:00
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module->remove(cell);
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}
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}
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}
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2019-08-12 14:06:45 -05:00
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}
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} Ice40WrapCarryPass;
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PRIVATE_NAMESPACE_END
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