skywater-pdk/docs/rules/periphery/periphery.csv

63 KiB

10 Errors10
2RuleSection G2: Design Rules for SKY130*Use
3sky130
4Section G2a. Periphery Rules
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6(x.-)General
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8
9The following are exempt from x.22 violations: _techCD_ , inductor.dg, modulecut, capacitors and s8blerf
10The 'notPublicCell' switch will deactivate this rule
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13Note: some rules contain correction factors to compensate possible mask defect and unpredicted process biases
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15(dnwell.-)Deep Nwellsky130
16Function: Define deep nwell for isolating pwell and noise immunity
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42(nwell.-)Nwellsky130
43Function: Define nwell implant regions
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45Nwells can merge over deep nwell if spacing too small (as in rule nwell.2)
46Spacing between nwell and deep nwell on the same net is set by the sum of the rules nwell.2 and nwell.5. By default, DRC run on a cell checks for the separate-net spacing, when nwell and deep nwell nets are separate within the cell hierarchy and are joined in the upper hierarchy. To allow net names to be joined and make the same-net rule applicable in this case, the "joinNets" switch should be turned on.
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49waffle_chip
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71(pwbm.-)Pwbmsky130
72Function: Define p-well block
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88(pwdem.-)Pwdemsky130
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110(hvtp.-)Hvtpsky130
111Function: Define Vt adjust implant region for high Vt LV PMOS;
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137(hvtr.-)Hvtrsky130
138Function: Define low VT adjust implant region for pmedlvtrf;
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142(lvtn.-)Lvtnmsky130
143Function: Define regions to block Vt adjust implant for low Vt LV PMOS/NMOS, SONOS FETs and Native NMOS
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177(ncm.-)Ncmsky130
178Function: Define Vt adjust implant region for LV NMOS in the core of NVSRAM
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192(difftap.-)Diff/tapsky130
193Function: Defines active regions and contacts to substrate
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219(tunm.-)Tunnelsky130
220Function: Defines SONOS FETs
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247(poly.-)Poly sky130
248Function: Defines FET gates, interconnects and resistors
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282(rpm.-)P+ Poly resistorsky130
283Function: Defines p+ poly resistors
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308(varac.-)Varactorsky130
309Function: Defines varactors
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334(photo.-)Photo diodesky130
335Function: Photo diode for sensing light
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362(npc.-)Nitride Poly Cut (NPC)sky130
363Function: Defines nitride openings to contact poly and Li1
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384(n/ psd.-)N+/P+ Source/Drain Implants (Nsdm and Psdm)sky130
385Function: Defines opening for N+/P+ implants
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399(licon.-)Local Interconnect Contact (Licon)sky130
400Function: Defines contacts between poly/diff/tap and Li1
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446(li.-.-)Local Interconnect (LI)sky130
447Function: Defines local interconnect to diff/tap and poly
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461(ct.-)Metal contact (Mcon)sky130
462Function: Defines contact between Li1 and met1
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474(capm.-)MIM Capacitor (Capm)sky130
475Function: Defines MIM capacitor
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501(vpp.-)VPP Capacitor sky130
502Function: Defines VPP capacitor
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527(m1.-)Met1sky130
528Function: Defines first level of metal interconnects, buses etc;
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556(via.-)Viasky130
557Function: Defines contact between met1 and met2
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573(m2.-)Metal 2sky130
574Function: Defines second level of metal interconnects, buses etc
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598(via2.-)Via2sky130
599Function: Via2 connects met2 to met3 in the SKY130T*/SKY130P*/SP8Q/SP8P* flows and met2/capm to met3 in the SKY130DI* flow.
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615(m3.-)Metal 3sky130
616Function: Defines third level of metal interconnects, buses etc
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636(via3.-)Via3sky130
637Function: Via3 connects met3 to met4 in the SKY130Q*/SKY130P*/SP8Q/SP8P* flow
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640(nsm.-)Nitride Seal Masksky130
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643(indm.-)Inductor metalsky130
644Function: Defines third level of metal interconnects, buses and inductor; top_indmMetal is met3 for SKY130D* flows; Similarly top_padVia is Via2 for SKY130D*
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656(m4.-)Metal 4sky130
657Function: Defines Fourth level of metal interconnects;
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686(via4.-)Via4sky130
687Function: Via4 connects met4 to met5 in the SKY130P*/SP8P* flow
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690(m5.-)Metal 5sky130
691Function: Defines Fifth level of metal interconnects;
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694(pad.-)Padsky130
695Function: Opens the passivation
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698(rdl.-)Cu Inductorsky130
699Function: Defines the Cu Inductor. Connects to met5 through the pad opening
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702(mf.-)Metal Fusesky130
703Function: Defines metal fuses
704For SKY130D* and SKY130TM* CADflow use MM2 for Metal Fuse
705For SP8P*/SKY130P* (PLM) CADflow use MM4 for Metal Fuse
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738(hvi.-)HVIsky130
739Function: Defines thick oxide for high voltage devices
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752(nwell.-)High Voltage Nwellsky130
753Function: Defines rules for HV nwell; All nwell connected to voltages greater than 1.8V must be enclosed by hvi; Nets connected to LV nwell or nwell overlapping hvi but connected to LV voltages (i.e 1.8V) should be tagged "lv_net" using text.dg; This tag should be only on Li layer
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769(difftap.-)High Voltage Diff/Tapsky130
770Function: Defines rules for HV diff/tap
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810(poly.-)High Voltage Polysky130
811Function: Defines rules for HV poly
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836(hvntm.-)Hvntmsky130
837Function: Defines tip implants for the HV NMOS
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868(denmos.-)Denmossky130
869Function: Defines rules for the 16V Drain extended NMOS devices
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895(depmos.-)Depmossky130
896Function: Defines rules for the 16V Drain extended NMOS devices
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924(extd.-)Extended Drainsky130
925Function: Defines rules :drc_tag:`areaid.en`
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940(hv.-.-)High Voltage Rulessky130
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1002(vhvi.-.-)VHVI - Very HV ID and Rulessky130
1003Function: Identify nets working between 12-16V
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1006(uhvi.-.-)UHVI - Ultra HV ID and Rulessky130
1007Function: Identify nets working between 20V
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1010(ulvt-.-):drc_tag:`areaid.low_vt` for UHV Diodes sky130
1011Function: Identify dnwdiodehv_Psub(BV~60V)
1012NA
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1014(pwres.-.-)Pwell resistorsky130
1015Function: Identify pwell resistors
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1041(rfdiode.-.-)Areaid.re for RF Diodes sky130
1042Function: Identify RF diodes; Used for RCX
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1046Allowed PNP layout
1047Layout: pnppar
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1072Allowed NPN layout
1073Layout: npnpar1x1
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