1a,"p1m.md (OPC), DECA and AMKOR layers (pi1.dg, pmm.dg, rdl.dg, pi2.dg, ubm.dg, bump.dg) and mask data for p1m, met1, via, met2 must be on a grid of mm",,0.001,mm
1b,Data for SKY130 layout and mask on all layers except those mentioned in 1a must be on a grid of mm (except inside Seal ring),,0.005,mm
2,Angles permitted on: diff,,N/A,N/A
,"Angles permitted on: diff except for:\n- diff inside ""advSeal_6µm* OR cuPillarAdvSeal_6µm*"" pcell, \n- diff rings around the die at min total L>1000 µm and W=0.3 µm",,n x 90,deg
,"Angles permitted on: tap (except inside :drc_tag:`areaid.en`), poly (except for ESD flare gates or gated_npn), li1(periphery), licon1, capm, mcon, via, via2. Anchors are exempted.",,n x 90,deg
,Angles permitted on: via3 and via4. Anchors are exempted.,,n x 90,deg
2a,Analog circuits identified by :drc_tag:`areaid.analog` to use rectangular diff and tap geometries only; that are not to be merged into more complex shapes (T's or L's),,,
2c,"45 degree angles allowed on diff, tap inside UHVI",,,
,,,
3,Angles permitted on all other layers and in the seal ring for all the layers,,,
3a,"Angles permitted on all other layers except WLCSP layers (pmm, rdl, pmm2, ubm and bump)",,n x 45,deg
4,Electrical DR cover layout guidelines for electromigration,NC,,
5,"All ""pin""polygons must be within the ""drawing"" polygons of the layer",Al,,
6,All intra-layer separation checks will include a notch check,,,
7,Mask layer line and space checks must be done on all layers (checked with s.x rules),NC,,
8,"Use of areaid ""core"" layer (""coreid"") must be approved by technology",NC,,
9,"Shapes on maskAdd or maskDrop layers (""serifs"") are allowed in core only. Exempted are: \n- cfom md/mp inside ""advSeal_6um* OR cuPillarAdvSeal_6um*"" pcell \n- diff rings around the die at min total L>1000 um and W=0.3 um, and PMM/PDMM inside areaid:sl",,,
,"Shapes on maskAdd or maskDrop layers (""serifs"") are allowed in core only. PMM/PDMM inside areaid:sl are excluded.",,N/A,N/A
10,"Res purpose layer for (diff, poly) cannot overlap licon1",,,
11,Metal fuses are drawn in met2,LVS,N/A,N/A
,Metal fuses are drawn in met3,LVS,N/A,N/A
,Metal fuses are drawn in met4,LVS,,
\n12a\n12b\n12c,"To comply with the minimum spacing requirement for layer X in the frame:\n- Spacing of :drc_tag:`areaid.mt` to any non-ID layer\n- Enclosure of any non-ID layer by :drc_tag:`areaid.mt`\n- Rules exempted for cells with name ""*_buildspace""",F,,
12d,- Spacing of :drc_tag:`areaid.mt` to huge_metX (Exempt met3.dg),F,N/A,N/A
12d,- Spacing of :drc_tag:`areaid.mt` to huge_metX (Exempt met5.dg),F,,
12e,- Enclosure of huge_metX by :drc_tag:`areaid.mt` (Exempt met3.dg),F,N/A,N/A
12e,- Enclosure of huge_metX by :drc_tag:`areaid.mt` (Exempt met5.dg),F,,
13,Spacing between features located across areaid:ce is checked by …,,,
14,Width of features straddling areaid:ce is checked by …,,,
15a,"Drawn compatible, mask, and waffle-drop layers are allowed only inside areaid:mt (i.e., etest modules), or inside areaid:sl (i.e., between the outer and inner areaid:sl edges, but not in the die) or inside areaid:ft (i.e., frame, blankings). Exception: FOM/P1M/Metal waffle drop are allowed inside the die",P,,
15b,"Rule X.15a exempted for cpmm.dg inside cellnames ""PadPLfp"", ""padPLhp"", ""padPLstg"" and ""padPLwlbi"" (for the SKY130di-5r-gsmc flow)",Exempt,,
16,"Die must not overlap :drc_tag:`areaid.mt` (rule waived for test chips and exempted for cellnames ""*tech_CD_*"", ""*_techCD_*"", ""lazX_*"" or ""lazY_*"" )",,,
17,"All labels must be within the ""drawing"" polygons of the layer; This check is enabled by using switch ""floating_labels""; Identifies floating labels which appear as warnings in LVS. Using this check would enable cleaner LVS run; Not a gate for tapeout",,,
18,"Use redundant mcon, via, via2, via3 and via4 (Locations where additional vias/contacts can be added to existing single vias/contacts will be identified by this rule).\nSingle via under :drc_tag:`areaid.core` and :drc_tag:`areaid.standarc` are excluded from the single via check",RR,,
19,"Lower left corner of the seal ring should be at origin i.e (0,0)",,,
20,"Min spacing between pins on the same layer (center to center); Check enabled by switch ""IP_block""",,,
21,prunde.dg is allowed only inside :drc_tag:`areaid.mt` or :drc_tag:`areaid.sc`,,,
22,"No floating interconnects (poly, li1, met1-met5) or capm allowed; Rule flags interconnects with no path to poly, difftap or metal pins. Exempt floating layers can be excluded using poly_float, li1_float, m1_float, m2_float, m3_float, m4_float and m5_float text labels. Also flags an error if these text labels are placed on connected layers (not floating) and if the labels are not over the appropriate metal layer. \nIf floating interconnects need to be connected at a higher level (Parent IP or Full chip), such floating interconnects can be exempted using poly_tie, li1_tie, m1_tie, m2_tie, m3_tie, m4_tie and m5_tie text labels.\nIt is the responsibility of the IP owner and chip/product owner to communicate and agree to the node each of these texted lines is connected to, if there is any risk to how a line is tied, and to what node.\nOnly metals outside :drc_tag:`areaid.stdcell` are checked.\n",RC,,
23a,:drc_tag:`areaid.sl` must not overlap diff,,N/A,N/A
23b,diff cannot straddle :drc_tag:`areaid.sl`,,,
23c,":drc_tag:`areaid.sl` must not overlap tap, poly, li1 and metX",,,
23d,":drc_tag:`areaid.sl` must not overlap tap, poly",,N/A,N/A
23e,"areaid:sl must not overlap li1 and metX for pcell ""advSeal_6um""",,N/A,N/A
23f,"areaid:SubstrateCut (:drc_tag:`areaid.st`, local_sub) must not straddle p+ tap",RR,,
24,condiode label must be in iso_pwell,,,
25,"pnp.dg must be only within cell name ""s8rf_pnp"", ""s8rf_pnp5x"" or ""s8tesd_iref_pnp"", ""stk14ecx_*""",,,
26,"""advSeal_6um"" pcell must overlap diff",,,
27,"If the sealring is present, then partnum is required. To exempt the requirement, place text.dg saying ""partnum_not_necessary"".\n""partnum*block"" pcell should be used instead of ""partnum*"" pcells",RR,N/A,N/A
28,Min width of :drc_tag:`areaid.sl`,,N/A,N/A
29,nfet must be enclosed by dnwell. Rule is checked when switch nfet_in_dnwell is turned on.,,,
,,,,
Use,Explanation,,,
P,Rule applies to periphery only (outside :drc_tag:`areaid.ce`). A corresponding core rule may or may not exist.,,,
NE,Rule not checked for esd_nwell_tap. There are no corresponding rule for esd_nwell_tap.,,,
NC,Rule not checked by DRC. It should be used as a guideline only.,,,
TC,"Rule not checked for cell name ""*_tech_CD_top*""",,,
A,Rule documents a functionality implemented in CL algorithms and may not be checked by DRC.,,,
AD,Rule documents a functionality implemented in CL algorithms and checked by DRC.,,,
DE,Rule not checked for source of Drain Extended device,,,
LVS,Rule handled by LVS,,,
F,"Rule intended for Frame only, not checked inside Die",,,
DNF,Drawn Not equal Final. The drawn rule does not reflect the final dimension on silicon. See table J for details.,,,
RC,"Recommended rule at the chip level, required rule at the IP level.",,,
RR,Recommended rule at any IP level,,,
Al Cu,Rules applicable only to Al or Cu BE flows,,,
IR,IR drop check compering Al database and slotted Cu database for the same product (2 gds files) must be clean,Cu,,
3,Min spacing between deep nwells. Rule exempt inside UHVI.,,6.300,µm
3a,Min spacing between deep nwells on same net inside UHVI.,,N/A,N/A
3b,Min spacing between deep-nwells inside UHVI and deep-nwell outside UHVI,,N/A,N/A
3c,Min spacing between deep-nwells inside UHVI and nwell outsideUHVI,,N/A,N/A
3d,Min spacing between deep-nwells inside UHVI on different nets,,N/A,N/A
4,Dnwell can not overlap pnp:dg,,,
5,P+_diff can not straddle Dnwell,,,
6,RF NMOS must be enclosed by deep nwell (RF FETs are listed in $DESIGN/config/tech/model_set/calibre/fixed_layout_model_map of corresponding techs),,,
,"Spacing between nwell and deep nwell on the same net is set by the sum of the rules nwell.2 and nwell.5. By default, DRC run on a cell checks for the separate-net spacing, when nwell and deep nwell nets are separate within the cell hierarchy and are joined in the upper hierarchy. To allow net names to be joined and make the same-net rule applicable in this case, the ""joinNets"" switch should be turned on.",,
2,"Minimum channel width (Diff And Poly) except for FETs inside :drc_tag:`areaid.sc`: Rule exempted in the SP8* flows only, for the cells listed in rule difftap.2a ",P,0.420,µm
2a,"Minimum channel width (Diff And Poly) for cell names ""s8cell_ee_plus_sseln_a"", ""s8cell_ee_plus_sseln_b"", ""s8cell_ee_plus_sselp_a"", ""s8cell_ee_plus_sselp_b"" , ""s8fpls_pl8"", ""s8fpls_rdrv4"" , ""s8fpls_rdrv4f"" and ""s8fpls_rdrv8""",P,NA,µm
2b,Minimum channel width (Diff And Poly) for FETs inside :drc_tag:`areaid.sc`,P,0.360,µm
3,"Spacing of diff to diff, tap to tap, or non-abutting diff to tap",,0.270,µm
4,Min tap bound by one diffusion,,0.290,
5,Min tap bound by two diffusions,P,0.400,
6,Diff and tap are not allowed to extend beyond their abutting edge,,,
7,Spacing of diff/tap abutting edge to a non-conciding diff or tap edge,NE,0.130,µm
8,Enclosure of (p+) diffusion by N-well. Rule exempted inside UHVI.,"DE, NE, P",0.180,µm
9,Spacing of (n+) diffusion to N-well outside UHVI,"DE, NE, P",0.340,µm
10,Enclosure of (n+) tap by N-well. Rule exempted inside UHVI.,"NE, P",0.180,µm
11,Spacing of (p+) tap to N-well. Rule exempted inside UHVI.,,0.130,µm
12,ESD_nwell_tap is considered shorted to the abutting diff,NC,,
13,Diffusion or the RF FETS in Table H5 is defined by Ldiff and Wdiff.,,,
X.1,All FETs would be checked for W/Ls as documented in spec 001-02735 (Exempt FETs that are pruned; exempt for W/L's inside :drc_tag:`areaid.sc` and inside cell name scs8*decap* and listed in the MRGA as a decap only W/L),,,
X.1a,Min & max dummy_poly L is equal to min L allowed for corresponding device type (exempt rule for dummy_poly in cells listed on Table H3),,,
1a,Width of poly,,0.150,µm
1b,Min channel length (poly width) for pfet overlapping lvtn (exempt rule for dummy_poly in cells listed on Table H3),,0.350,µm
2,Spacing of poly to poly except for poly.c2 and poly.c3; Exempt cell: sr_bltd_eq where it is same as poly.c2,,0.210,µm
3,Min poly resistor width,,0.330,µm
4,Spacing of poly on field to diff (parallel edges only),P,0.075,µm
5,Spacing of poly on field to tap,P,0.055,µm
6,Spacing of poly on diff to abutting tap (min source),P,0.300,µm
7,Extension of diff beyond poly (min drain),P,0.250,
8,Extension of poly beyond diffusion (endcap),P,0.130,
9,Poly resistor spacing to poly or spacing (no overlap) to diff/tap,,0.480,µm
10,Poly can't overlap inner corners of diff,,,
11,No 90 deg turns of poly on diff,,,
12,"(Poly NOT (nwell NOT hvi)) may not overlap tap; Rule exempted for cell name ""s8fgvr_n_fg2"" and gated_npn and inside UHVI.",P,,
15,Poly must not overlap diff:rs,,,
16,"Inside RF FETs defined in Table H5, poly cannot overlap poly across multiple adjacent instances",,,
1g,Only 1 licon is allowed in xhrpoly_0p35 prec_resistor_terminal,,,
1h,Only 1 licon is allowed in xhrpoly_0p69 prec_resistor_terminal,,,
1i,Only 2 licons are allowed in xhrpoly_1p41 prec_resistor_terminal,,,
1j,Only 4 licons are allowed in xhrpoly_2p85 prec_resistor_terminal,,,
1k,Only 8 licons are allowed in xhrpoly_5p73 prec_resistor_terminal,,,
2,Min spacing of rpm to rpm,,0.840,µm
3,rpm must enclose prec_resistor by atleast,,0.200,
4,prec_resistor must be enclosed by psdm by atleast,,0.110,µm
5,prec_resistor must be enclosed by npc by atleast,,0.095,µm
6,"Min spacing, no overlap, of rpm and nsdm",,0.200,µm
7,Min spacing between rpm and poly,,0.200,µm
8,poly must not straddle rpm,,,
9,"Min space, no overlap, between prec_resistor and hvntm",,0.185,µm
10,Min spacing of rpm to pwbm,,N/A,N/A
11,rpm should not overlap or straddle pwbm except cells\ns8usbpdv2_csa_top\ns8usbpdv2_20vconn_sw_300ma_ovp_ngate_unit\ns8usbpdv2_20vconn_sw_300ma_ovp\ns8usbpdv2_20sbu_sw_300ma_ovp,,N/A,N/A
5a,"Enclosure of diff by nsdm(psdm), except for butting edge",,0.125,µm
5b,"Enclosure of tap by nsdm(psdm), except for butting edge",P,0.125,µm
6,Enclosure of diff/tap butting edge by nsdm (psdm),,0.000,µm
7,Spacing of NSDM/PSDM to opposite implant diff or tap (for non-abutting diff/tap edges),,0.130,µm
8,Nsdm and psdm cannot overlap diff/tap regions of opposite doping,DE,,
9,"Diff and tap must be enclosed by their corresponding implant layers. Rule exempted for\n- diff inside ""advSeal_6um* OR cuPillarAdvSeal_6um*"" pcell for SKY130P*/SP8P*/SKY130DI-5R-CSMC flows\n- diff rings around the die at min total L>1000 um and W=0.3 um\n- gated_npn \n- :drc_tag:`areaid.zer`.",DE,,
1,Min and max L and W of licon (exempt licons inside prec_resistor),,0.170,µm
1b,Min and max width of licon inside prec_resistor,,0.190,µm
1c,Min and max length of licon inside prec_resistor,,2.000,µm
2,Spacing of licon to licon,P,0.170,µm
2b,Min spacing between two slotted_licon (when the both the edges are 0.19um in length),,0.350,µm
2c,Min spacing between two slotted_licon (except for rule licon.2b),,0.510,µm
2d,Min spacing between a slotted_licon and 0.17um square licon,,0.510,µm
3,Only min. square licons are allowed except die seal ring where licons are (licon CD)*L,,0.170 *L,
4,Licon1 must overlap li1 and (poly or diff or tap),,,
5a,Enclosure of licon by diff,P,0.040,µm
5b,Min space between tap_licon and diff-abutting tap edge,P,0.060,µm
5c,Enclosure of licon by diff on one of two adjacent sides,P,0.060,µm
6,Licon cannot straddle tap,P,,
7,Enclosure of licon by one of two adjacent edges of isolated tap,P,0.120,µm
8,Enclosure of poly_licon by poly,P,0.050,µm
8a,Enclosure of poly_licon by poly on one of two adjacent sides,P,0.080,µm
9,"Spacing, no overlap, between poly_licon and psdm; In SKY130DIA/SKY130TMA/SKY130PIR-10 flows, the rule is checked only between (poly_licon outside rpm) and psdm",P,0.110,µm
10,Spacing of licon on (tap AND (nwell NOT hvi)) to Var_channel,P,0.250,µm
11,"Spacing of licon on diff or tap to poly on diff (except for all FETs inside :drc_tag:`areaid.sc` and except s8spf-10r flow for 0.5um phv inside cell names ""s8fs_gwdlvx4"", ""s8fs_gwdlvx8"", ""s8fs_hvrsw_x4"", ""s8fs_hvrsw8"", ""s8fs_hvrsw264"", and ""s8fs_hvrsw520"" and for 0.15um nshort inside cell names ""s8fs_rdecdrv"", ""s8fs_rdec8"", ""s8fs_rdec32"", ""s8fs_rdec264"", ""s8fs_rdec520"")",P,0.055,µm
11a,Spacing of licon on diff or tap to poly on diff (for all FETs inside :drc_tag:`areaid.sc` except 0.15um phighvt),P,0.050,µm
11b,Spacing of licon on diff or tap to poly on diff (for 0.15um phighvt inside :drc_tag:`areaid.sc`),P,0.050,µm
11c,"Spacing of licon on diff or tap to poly on diff (for 0.5um phv inside cell names ""s8fs_gwdlvx4"", ""s8fs_gwdlvx8"", ""s8fs_hvrsw_x4"", ""s8fs_hvrsw8"", ""s8fs_hvrsw264"", and ""s8fs_hvrsw520"")",P,0.040,µm
11d,"Spacing of licon on diff or tap to poly on diff (for 0.15um nshort inside cell names ""s8fs_rdecdrv"", ""s8fs_rdec8"", ""s8fs_rdec32"", ""s8fs_rdec264"", ""s8fs_rdec520"")",P,0.045,µm
12,Max SD width without licon,NC,5.700,µm
13,Spacing (no overlap) of NPC to licon on diff or tap,P,0.090,µm
14,Spacing of poly_licon to diff or tap,P,0.190,µm
15,poly_licon must be enclosed by npc by…,P,0.100,µm
16,"Every source_diff and every tap must enclose at least one licon1, including the diff/tap straddling areaid:ce. \nRule exempted inside UHVI.",P,,
17,Licons may not overlap both poly and (diff or tap),,,
18,Npc must enclose poly_licon,,,
19,poly of the HV varactor must not interact with licon,P,,
1a,Width of LI inside of cells with name s8rf2_xcmvpp_hd5_*,P,0.140,µm
2,Max ratio of length to width of LI without licon or mcon,NC,10.000,µm
3,Spacing of LI to LI (except for li.3a),P,0.170,µm
3a,Spacing of LI to LI inside cells with names s8rf2_xcmvpp_hd5_*,P,0.140,µm
5,Enclosure of licon by one of two adjacent LI sides,P,0.080,µm
6,Min area of LI,P,0.0561,µm²
7,"Min LI resistor width (rule exempted within :drc_tag:`areaid.ed`; Inside :drc_tag:`areaid.ed`, min width of the li resistor is determined by rule li.1)",,0.290,µm
1b,Max width of capacitor:dg; Rule not applicable for vpp_with_Met3Shield and vpp_with_LiShield and vpp_over_MOSCAP and vpp_with_Met5 and vpp_with_noLi,,11.350,µm
1c,"Min/Max width of cell name ""s8rf_xcmvpp1p8x1p8_m3shield """,,3.880,µm
3,"capacitor:dg must not overlap (tap or diff or poly); (one exception: Poly is allowed to overlap vpp_with_Met3Shield and vpp_with_Met5PolyShield); (not applicable for vpp_over_Moscap or ""s8rf2_xcmvppx4_2xnhvnative10x4"" or vpp_with_LiShield)",,,
4,capacitor:dg must not straddle (nwell or dnwell),,,
5,Min spacing between (capacitor:dg edge and (poly or li1 or met1 or met2)) to (poly or li1 or met1 or met2) on separate nets (Exempt area of the error shape less than 2.25 µm² and run length less than 2.0um); Rule not applicable for vpp_with_Met3Shield and vpp_with_LiShield and vpp_over_MOSCAP and vpp_with_Met5 and vpp_with_noLi,,1.500,µm
5a,Max pattern density of met3.dg over capacitor.dg (not applicable for vpp_with_Met3Shield and vpp_with_LiShield and vpp_over_MOSCAP and vpp_with_Met5),,0.25,\-
5b,Max pattern density of met4.dg over capacitor.dg (not applicable for vpp_with_Met3Shield and vpp_with_Met5 and vpp_over_MOSCAP),,0.3,\-
5c,"Max pattern density of met5.dg over capacitor.dg (not applicable for vpp_with_Met3Shield and vpp_with_Met5 and vpp_over_MOSCAP and vpp_with_noLi); (one exception: rules does apply to cell ""s8rf2_xcmvpp11p5x11p7_m1m4"" and ""s8rf2_xcmvpp_hd5_atlas*"")",,0.4,\-
8,Min enclosure of capacitor:dg by nwell,,1.500,µm
9,Min spacing of capacitor:dg to nwell (not applicable for vpp_over_MOSCAP),,1.500,µm
10,vpp capacitors must not overlap; Rule checks for capacitor.dg overlapping more than one pwell pin,,,
11,Min pattern density of (poly and diff) over capacitor.dg; (vpp_over_Moscap only),,0.87,\-
12a,"Number of met4 shapes inside capacitor.dg of cell ""s8rf2_xcmvpp8p6x7p9_m3_lim5shield"" must overlap with size 2.01 x 2.01 (no other met4 shapes allowed)",,9.00,µm
12b,"Number of met4 shapes inside capacitor.dg of cell ""s8rf2_xcmvpp11p5x11p7_m3_lim5shield"" must overlap with size 2.01 x 2.01 (no other met4 shapes allowed)",,16.00,µm
12c,"Number of met4 shapes inside capacitor.dg of cell ""s8rf2_xcmvpp4p4x4p6_m3_lim5shield"" must overlap with size 1.5 x 1.5 (no other met4 shapes allowed)",,4.00,µm
13,Min space of met1 to met1inside VPP capacitor,Cu,0.160,µm
14,Min space of met2 to met2 inside VPP capacitor,Cu,0.160,µm
.X.1,"Algorithm should flag errors, for met1, if ANY of the following is true:\nAn entire 700x700 window is covered by cmm1 waffleDrop, and metX PD < 70% for same window.\n80-100% of 700x700 window is covered by cmm1 waffleDrop, and metX PD < 65% for same window.\n60-80% of 700x700 window is covered by cmm1 waffleDrop, and metX PD < 60% for same window.\n50-60% of 700x700 window is covered by cmm1 waffleDrop, and metX PD < 50% for same window.\n40-50% of 700x700 window is covered by cmm1 waffleDrop, and metX PD < 40% for same window.\n30-40% of 700x700 window is covered by cmm1 waffleDrop, and metX PD < 30% for same window.\nExclude cells whose area is below 40Kum2. NOTE: Required for IP, Recommended for Chip-level.",RC,,
1,Width of metal1,,0.140,µm
2,Spacing of metal1 to metal1,,0.140,µm
3a,Min. spacing of features attached to or extending from huge_met1 for a distance of up to 0.280 µm to metal1 (rule not checked over non-huge met1 features),,0.280,µm
3b,Min. spacing of huge_met1 to metal1 excluding features checked by m1.3a,,0.280,µm
4,Mcon must be enclosed by Met1 by at least …(Rule exempted for cell names documented in rule m1.4a),P,0.030,µm
4a,"Mcon must be enclosed by Met1 by at least (for cell names ""s8cell_ee_plus_sseln_a"", ""s8cell_ee_plus_sseln_b"", ""s8cell_ee_plus_sselp_a"", ""s8cell_ee_plus_sselp_b"", ""s8fpls_pl8"", and ""s8fs_cmux4_fm"")",P,0.005,µm
5,Mcon must be enclosed by Met1 on one of two adjacent sides by at least …,"P, Al",0.060,µm
.X.1,"Algorithm should flag errors, for met2, if ANY of the following is true:\nAn entire 700x700 window is covered by cmm2 waffleDrop, and metX PD < 70% for same window.\n80-100% of 700x700 window is covered by cmm2 waffleDrop, and metX PD < 65% for same window.\n60-80% of 700x700 window is covered by cmm2 waffleDrop, and metX PD < 60% for same window.\n50-60% of 700x700 window is covered by cmm2 waffleDrop, and metX PD < 50% for same window.\n40-50% of 700x700 window is covered by cmm2 waffleDrop, and metX PD < 40% for same window.\n30-40% of 700x700 window is covered by cmm2 waffleDrop, and metX PD < 30% for same window.\nExclude cells whose area is below 40Kum2. Required for IP, Recommended for Chip-level.",RC,,
1,Width of metal 2,,0.140,µm
2,Spacing of metal 2 to metal 2,,0.140,µm
3a,Min. spacing of features attached to or extending from huge_met2 for a distance of up to 0.280 µm to metal2 (rule not checked over non-huge met2 features),,0.280,µm
3b,Min. spacing of huge_met2 to metal2 excluding features checked by m2.3a,,0.280,µm
3c,"Min spacing between floating_met2 with AR_met2_A >= 0.05 and AR_met2_B =< 0.032, outside areaid:sc must be greater than",RR,0.145,µm
4,Via must be enclosed by Met2 by at least …,"P, Al",0.055,µm
5,Via must be enclosed by Met2 on one of two adjacent sides by at least …,Al,0.085,µm
6,Min metal2 area ,,0.0676,µm²
7,Min area of metal2 holes ,,0.140,µm²
pd.1,Min MM2_oxide_Pattern_density,RR,0.7,\-
pd.2a,Rule m2.pd.1 has to be checked by dividing the chip into square regions of width and length equal to …,A,700,µm
pd.2b,Rule m2.pd.1 has to be checked by dividing the chip into steps of …,A,70,
11,Max width of metal2,Cu,4.000,µm
12,Add slots and remove vias and contacts if met2 wider than…..,Cu,3.200,
13,Max pattern density (PD) of metal2,Cu,0.77,\-
14,Met2 PD window size,Cu,50.000,µm
14a,Met2 PD window step,Cu,25.000,µm
15,Via must be enclosed by met2 by at least…,Cu,0.040,µm
.X.1,"Algorithm should flag errors, for met3, if ANY of the following is true:\nAn entire 700x700 window is covered by cmm3 waffleDrop, and metX PD < 70% for same window.\n80-100% of 700x700 window is covered by cmm3 waffleDrop, and metX PD < 65% for same window.\n60-80% of 700x700 window is covered by cmm3 waffleDrop, and metX PD < 60% for same window.\n50-60% of 700x700 window is covered by cmm3 waffleDrop, and metX PD < 50% for same window.\n40-50% of 700x700 window is covered by cmm3 waffleDrop, and metX PD < 40% for same window.\n30-40% of 700x700 window is covered by cmm3 waffleDrop, and metX PD < 30% for same window.\nExclude cells whose area is below 40Kum2. NOTE: Required for IP, Recommended for Chip-level.",RC,,
1,Width of metal 3,,0.300,µm
2,Spacing of metal 3 to metal 3,,0.300,µm
3a,Min. spacing of features attached to or extending from huge_met3 for a distance of up to 0.480 um to metal3 (rule not checked over non-huge met3 features),,N/A,N/A
3b,Min. spacing of huge_met3 to metal3 excluding features checked by m3.3a,,N/A,N/A
3c,Min. spacing of features attached to or extending from huge_met3 for a distance of up to 0.400 µm to metal3 (rule not checked over non-huge met3 features),,0.400,µm
3d,Min. spacing of huge_met3 to metal3 excluding features checked by m3.3a,,0.400,µm
4,Via2 must be enclosed by Met3 by at least …,Al,0.065,µm
5,Via2 must be enclosed by Met3 on one of two adjacent sides by at least …,,N/A,N/A
5a,Via2 must be enclosed by Met3 on all sides by at least …(Rule not checked on a layout when it satisfies both rules m3.4 and m3.5),,N/A,N/A
6,Min area of metal3,,0.240,µm²
7,Min area of metal3 holes ,Cu,0.200,µm²
pd.1,Min MM3_oxide_Pattern_density,RR,0.7,\-
pd.2a,Rule m3.pd.1 has to be checked by dividing the chip into square regions of width and length equal to …,A,700,µm
pd.2b,Rule m3.pd.1 has to be checked by dividing the chip into steps of …,A,70,
11,Max width of metal3,Cu,4.000,µm
12,Add slots and remove vias and contacts if wider than…..,Cu,3.200,
13,Max pattern density (PD) of metal3,Cu,0.77,\-
14,Met3 PD window size,Cu,50.000,µm
14a,Met3 PD window step,Cu,25.000,µm
15,Via2 must be enclosed by met3 by at least…,Cu,0.060,µm
3,"Min spacing, no overlap, between NSM_keepout to diff.dg, tap.dg, fom.dy, cfom.dg, cfom.mk, poly.dg, p1m.mk, li1.dg, cli1m.mk, metX.dg (X=1 to 5) and cmmX.mk (X=1 to 5). Exempt the following from the check: (a) cell name ""nikon*"" and (b) diff ring inside :drc_tag:`areaid.sl` ",Al,1.000,µm
3a,"Min enclosure of diff.dg, tap.dg, fom.dy, cfom.dg, cfom.mk, poly.dg, p1m.mk, li1.dg, cli1m.mk, metX.dg (X=1 to 5) and cmmX.mk (X=1 to 5) by :drc_tag:`areaid.ft`. Exempt the following from the check: (a) cell name ""s8Fab_crntic*"" (b) blankings in the frame (rule uses :drc_tag:`areaid.dt` for exemption)",,3.000,µm
3b,"Min spacing between :drc_tag:`areaid.dt` to diff.dg, tap.dg, fom.dy, cfom.dg, cfom.mk, poly.dg, p1m.mk, li1.dg, cli1m.mk, metX.dg (X=1 to 5) and cmmX.mk (X=1 to 5). Exempt the following from the check: (a) blankings in the frame (rule uses :drc_tag:`areaid.dt` for exemption)",,3.000,µm
,"Function: Defines third level of metal interconnects, buses and inductor; top_indmMetal is met3 for SKY130D* flows; Similarly top_padVia is Via2 for SKY130D*",,
.X.1,"Algorithm should flag errors, for met4, if ANY of the following is true:\nAn entire 700x700 window is covered by cmm4 waffleDrop, and metX PD < 70% for same window.\n80-100% of 700x700 window is covered by cmm4 waffleDrop, and metX PD < 65% for same window.\n60-80% of 700x700 window is covered by cmm4 waffleDrop, and metX PD < 60% for same window.\n50-60% of 700x700 window is covered by cmm4 waffleDrop, and metX PD < 50% for same window.\n40-50% of 700x700 window is covered by cmm4 waffleDrop, and metX PD < 40% for same window.\n30-40% of 700x700 window is covered by cmm4 waffleDrop, and metX PD < 30% for same window.\nExclude cells whose area is below 40Kum2. Required for IP, Recommended for Chip-level.",RC,,
1,Min width of met4,,0.300,µm
2,Min spacing between two met4,,0.300,µm
3,via3 must be enclosed by met4 by atleast,Al,0.065,µm
4,Min area of met4 (rule exempted for probe pads which are exactly 1.42um by 1.42um),,N/A,N/A
4a,Min area of met4,,0.240,µm²
5a,Min. spacing of features attached to or extending from huge_met4 for a distance of up to 0.400 µm to metal4 (rule not checked over non-huge met4 features),,0.400,µm
5b,Min. spacing of huge_met4 to metal4 excluding features checked by m4.5a,,0.400,µm
7,Min area of meta4 holes ,Cu,0.200,µm²
pd.1,Min MM4_oxide_Pattern_density,RR,0.7,\-
pd.2a,Rule m4.pd.1 has to be checked by dividing the chip into square regions of width and length equal to …,A,700,µm
pd.2b,Rule m4.pd.1 has to be checked by dividing the chip into steps of …,A,70,
11,Max width of metal4,Cu,10.000,µm
12,Add slots and remove vias and contacts if wider than…..,Cu,10.000,
13,Max pattern density (PD) of metal4; met4 overlapping pdm areas are excluded from the check,Cu,0.77,\-
14,Met4 PD window size,Cu,50.000,µm
14a,Met4 PD window step,Cu,25.000,µm
15,Via3 must be enclosed by met4 by at least…,Cu,0.060,µm
3,"Min enclosure of pad by rdl, except rdl interacting with bump",,10.750,µm
4,Min spacing between rdl and outer edge of the seal ring,,15.000,µm
5,(rdl OR ccu1m.mk) must not overlap :drc_tag:`areaid.ft`. Exempt the following from the check: (a) blankings in the frame (rule uses :drc_tag:`areaid.dt` for exemption),,,
6,"Min spacing of rdl to pad, except rdl interacting with bump",,19.660,µm
,"Function: Defines rules for HV nwell; All nwell connected to voltages greater than 1.8V must be enclosed by hvi; Nets connected to LV nwell or nwell overlapping hvi but connected to LV voltages (i.e 1.8V) should be tagged ""lv_net"" using text.dg; This tag should be only on Li layer",,
8,Min space between HV_nwell and any nwell on different nets,,2.000,µm
9,(Nwell overlapping hvi) must be enclosed by hvi,,,
10,"LVnwell and HnWell should not be on the same net (for the purposes of this check, short the connectivity through resistors); Exempt HnWell with li nets tagged ""lv_net"" using text.dg and Hnwell connected to nwell overlapping :drc_tag:`areaid.hl`",TC,,
11,"Nwell connected to the nets mentioned in the ""Power_Net_Hv"" field of the latcup GUI must be enclosed by hvi (exempt nwell inside :drc_tag:`areaid.hl`). Also for the purposes of this check, short the connectivity through resistors. The rule will be checked in the latchup run and exempted for cells ""s8tsg5_tx_ibias_gen"" and ""s8bbcnv_psoc3p_top_18"", ""rainier_top, indus_top*"", ""rainier_top, manas_top, ccg3_top""",,,
Note,High voltage rule apply for an operating voltage range of 5.5 - 12V; Nodes switching between 0 to 5.5V do not need to follow these rules,,,
.X.1,High voltage source/drain regions must be tagged by diff:hv,,,
.X.3,"High voltage poly can be drawn over multiple diff regions that are ALL reverse-biased by at least 300 mV (existence of reverse-bias is not checked by the CAD flow). It can also be drawn over multiple diffs when all sources and all drain are shorted together. In these case, the high voltage poly can be tagged with the text:dg label with a value “hv_bb”. Exceptions to this use of the hv_bb label must be approved by technology. Under certain bias conditions, high voltage poly tagged with hv_bb can cross an nwell boundary. The poly of the drain extended device crosses nwell by construction and can be tagged with the ""hv_bb"" label. Use of the hv_bb label on high voltage poly crossing an nwell boundary must be approved by technology. All high voltage poly tagged with hv_bb will not be checked to hv.poly.1, hv.poly.2, hv.poly.3 and hv.poly.4.",,,
.X.4,Any piece of layout that is shorted to hv_source/drain becomes a high voltage feature.,,,
.X.5,"In cases where an hv poly gate abuts only low voltage source and drain, the poly gate can be tagged with the text:dg label with a value ""hv_lv"". In this case, the ""hv_lv"" tagged poly gate and its extensions will not be checked to hv.poly.6, but is checked by rules in the poly.-.- section. The use of the hv_lv label must be approved by technology.",,,
.X.6,"Nwell biased at voltages >= 7.2V must be tagged with text ""shv_nwell""",NC,,
.nwell.1,"Min spacing of nwell tagged with text ""shv_nwell"" to any nwell on different nets",,2.500,µm
.diff.1a,Minimum hv_source/drain spacing to diff for edges of hv_source/drain and diff not butting tap,,0.300,µm
.diff.1b,Minimum spacing of (n+/p+ diff resistors and diodes) connected to hv_source/drain to diff,,0.300,µm
.diff.2,Minimum spacing of nwell connected to hv_source/drain to n+ diff,DE,0.430,µm
.diff.3a,Minimum n+ hv_source/drain spacing to nwell,,0.550,µm
.diff.3b,Minimum spacing of (n+ diff resistors and diodes) connected to hv_source/drain to nwell,,0.550,µm
.poly.1,Hv poly feature hvPoly (including hv poly resistors) can be drawn over only one diff region and is not allowed to cross nwell boundary except (1) as allowed in rule .X.3 and (2) nwell hole boundary in depmos,,,
.poly.2,Min spacing of hvPoly (including hv poly resistor) on field to diff (diff butting hvPoly are excluded),,0.300,µm
.poly.3,Min spacing of hvPoly (including hv poly resistor) on field to n-well (exempt poly stradding nwell in a denmos/depmos),,0.550,µm
.poly.4,Enclosure of hvPoly (including hv poly resistor) on field by n-well (exempt poly stradding nwell in a denmos/depmos),,0.300,µm
.poly.6a,Min extension of poly beyond hvFET_gate (exempt poly extending beyond diff along the S/D direction in a denmos/depmos),,0.160,
.poly.6b,Extension of hv poly beyond FET_gate (including hvFET_gate; exempt poly extending beyond diff along the S/D direction in a denmos/depmos),,0.160,
.poly.7,Minimum overlap of hv poly ring_FET and diff,,,
.poly.8,Any poly gate abutting hv_source/drain becomes a hvFET_gate,,,
.vhv.1,Terminals operating at nominal 12V (maximum 16V) bias must be tagged as Very-High-Voltage (VHV) using vhvi:dg layer,,NC,
.vhv.2,A source or drain of a drain-extended device can be tagged by vhvi:dg. A device with either source or drain (not both) tagged with vhvi:dg serves as a VHV propagation stopper,,NC,
.vhv.3,Any feature connected to VHVSourceDrain becomes a very-high-voltage feature,,NC,
.vhv.4,Any feature connected to VHVPoly becomes a very-high-voltage feature,,NC,
.vhv.5,"Diffusion that is not a part of a drain-extended device (i.e., diff not areaid:en) must not be on the same net as VHVSourceDrain. Only diffusion inside :drc_tag:`areaid.ed` and LV diffusion tagged with vhvi:dg are exempted.",,,
.vhv.6,"Poly resistor can act as a VHV propagation stopper. For this, it should be tagged with text ""vhv_block""",,NC,
1,Min width of vhvi:dg,,0.020,µm
2,Vhvi:dg cannot overlap areaid:ce,,,
3,VHVGate must overlap hvi:dg,,,
4,Poly connected to the same net as a VHVSourceDrain must be tagged with vhvi:dg layer,,,
5,Vhvi:dg cannot straddle VHVSourceDrain,,,
6,Vhvi:dg overlapping VHVSourceDrain must not overlap poly,,,
7,Vhvi:dg cannot straddle VHVPoly,,,
8,"Min space between nwell tagged with vhvi:dg and deep nwell, nwell, or n+diff on a separate net (except for n+diff overlapping nwell tagged with vhvi:dg).",,11.240,µm
