skywater-pdk/docs/rules/assumptions/08-hv.csv

1	Layer / Design rule	CD		space		Comment
2	Min HVNwell to any nwell space			2		HVNwell_Nwell_SP
3	Min HVDiff width	0.29				HVDiff_CD
4	Min HVDiff space			0.3		HVDiff_SP
5	Min HV Pmos gate width	0.5				HVP_gate_CD
6	Min space between HV poly			0.28		HVPoly_SP
7	Min HV Nmos gate width	0.37				HVPoly_CD
8	HV P+ Diff enclosure by Nwell	0.33				HVPdiff_nwell_enc
9	HV N+ diff space to Nwell			0.43		HVNdiff_nwell_SP
10	HV N+ tap enclosure by Nwell	0.33				HVNtap_nwell_enc
11	HV P+tap space to Nwell			0.43		HVPtap_nwell_SP
12	Photoresist tilted implant penetration	0.02				HVPrPenetration
13	Photoresist tilted implant blocking distance	0.013				HVPrBlocking
14	Min size of HVTip	0.1				HVTipMinSize
15	Extra CD tol for HVNTM to match Ram7 process	0.015				HVNTMExtraCdTol
16	Min HVDiff resistor width	0.29				HVDiff_Res_CD
17	High voltage n+-n+ or p+-p+			0.3		HVDPTS15
18	HV MOSFET channel length	0.5				HVPCD