skywater-pdk/docs/rules/assumptions/07-other.csv

1	Layer / Design rule	CD		space		Comment
2	MOSFET width	0.135				FOMSE
3	MOSFET width in standard cells	0.075				FOMSESC
4	Spacing of poly on field to diff			0.065		PFDSE
5	Spacing of poly on field to tap			0.005		PFTSE
6	Enclosure of tap by nwell for pwell res			0.22		PTAP_NWL_SP
7	Grid conversion rounding factor			0.005		GRCF
8	Licon enclosure rounding			0.02		LICENCLR
9	LI1CD add/drop	0.01		0.04
10	Huge metal X min. W and L	3				HugeM
11	Min Nsdm area	0.265				MinNsdmArea
12	Min Psdm area	0.255				MinPsdmArea
13	Min N/Psdm hole area	0.265				MinNPsdmHole
14	Large waffle size must be divisible by 4	7.2				waffle_large
15	P1M additional CD control	0.011				P1MCDcontrol
16	Li1 proximity correction			0.25		LI1PROXSpace
17	Serif added to nwell convex corner (SXX-572, 573)	0.22				NwellCvxSerif
18	Serif added to nwell concave corner (SXX-572, 573)	0.12				NwellCveSerif
19	NWM extension beyond nwell edge straddling de_nFet_source (for GSMC; QZM-133)	0.075				NvhvNwellExt
20	Min enclosure of pad by pmm for Cu inductor (JNET-80)	0				padPMMEncInd
21	Min enclosure of pmm by cu1m for Cu inductor (JNET-80)	10.75				pmmCu1mEncInd
22	Min enclosure of pbo by cu1m per DECA 000348 Rev S	10				pboCu1mEnc
23	Min enclosure of pmm by pmm2 for radio flow in the die (JNET-80)	13				pmmPmm2EncInd
24	Min enclosure of pmm by pmm2 inside frame	7.5				pmmPmm2EncIndFrame
25	Min space between pmm2 and Inductor.dg			7.5		pmm2IndSpc
26	Min cu1m PD across full chip	0.35				MinCU1Mpd
27	Max cu1m PD across full chip	0.45				MaxCU1Mpd
28	Spacing between RDL and outer edge of seal ring	15				RdlSealSpc
29	Spacing between RDL and pmm2	6.16				RdlPmm2Spc
30	Enclosure of etest module in die by cpmm2	0				EtestCpmm2Enc
31	Keepout of active, poly, li and metal to NSM (TCS-2253)			1		NSMKeepout
32	3 um keepout of active, poly, li and metal to areaid.dt/areaid.ft (TCS-2253)			3		NSMKeepout_3um
33	pnp_emitter sizing (S8P GSMC flow)			0.05		PnpEmitterSzGSMC
34	pnp_emitter sizing (other flows)			0.03		PnpEmitterSz
35	MiM Capacitor aspect ration	20				MiM_AR
36	Min NCM space to be used to preserve NCM CL algorithm (avoid LVL error)			1.27		NCM_0LVL
37	Min space of NCM between core and periphery due to existing layout restriction			0.96		NcmCorePeriSP
38	Multiplication factor			0.01		S8LVconv
39	Minimum scribe width	50				scribew
40	spacing of p-well outside deep n-well to deep n-well mask edge			0.12		NWDNWENCL
41	p-well in deep n-well to p-sub			1.2		NWDNWOL
42	Field oxide etchback after P1ME before implants			0.04		WFDEL