Formerly, the H-Track could be shifted *relative* to the position of
the center of the RoutingPad. Which may become fragile in case of a
change in the standard cell library. So we create a new feature allowing
to specify the H-track as an offset *from the bottom of the slice*.
Two offset can be specified:
* spares.htreeOffsetDriver : for the main H part, connected to the
driver.
* spares.htreeOffsetSink : for the small parts connecting to every
fours sinks of the tree.
This to avoid those two to overlap. The sink of the "N" stage with
the driver of the "N+1" stage (so input & ouput of the same buffer).
* Switch back to a generated version of the documentation.
Dependencies for the documentation generation have been added to poetry.
As Pelican is a Python tool, that makes sense.
Note to myself: To generate the doc with ccb.py we *need* to be inside
the Python virtual env generated by Poetry. Instead of
relying of a default one, provide one of our own
(coriolis-venv) and make poetry run in it.
* Top builder.py now generated the doc.
* Forgot to remove generated PDFs in the documentation.
* A bit of cleanup on the README.rst
* Forgot the logo. Try to use code-block directive in README.
* Still typo in the logo path.
* One more trial at setting the image position.
* OK. That's enough for the logo.
* Problems with code-block.
* Voila!
* Build inside a venv and use poetry in the top level Makefile.
* Remove doxygen generated docs.
* More doc cleanup in oroshi.
* Change: In cumulus.plugins.core2chip.CoreToChip, add new methods:
* hasCornerCell() (return False)
* hasFillerCells() (return False)
* getCornerCell() (raise NotImplementedError)
* createSpacer() (raise NotImplementedError)
* createCorner() (raise NotImplementedError)
Those methods needs to be overloaded in derived classes when I/O spacers
and corner cells are supplied.
In IoPad, add a NON_CONNECT case for dummy pad that are not connected.
* New: In cumulus.plugins.chip.pads, delegate spacer & corner creation to
the coreToChip concrete class.
* New: In cumulus.plugins.block.configuration.IoPadConf, add support for
non-connected (dummy) pads.
Formerly, CoreToChip was seen as building the top-level netlist of the
chip only. But, when using special spacer pads, we need to have access
to that specific information from inside the Chip pads builder.
So we now move CoreToChip as an internal part of Chip. The right
CoreToChip to use (techno dependant) must be given as a configuration
parameter:
"conf.coreToChipClass"
It is the class, not an object that must be suplied.
* Bug: In LefImport::_macroCbk(), the GDS file must be loaded *before*
we start putting nets & components from the LEF file. The GDS parser
must find an blank slate and not try to modifies nets already
created by LEF.
This way, we really can modify the GDS layout to suit the LEF
statements.
Note that we may end up with two set of terminal exactly overlapping,
a Pad from the GDS and a Segment from LEF.
* Change: In GdsParser::xyToPath(), we were creating articulated layout
segments over contacts using the "all_nets_merged_in_gds" common net.
But some segment may later be promoted to interface, that means
deleting the previous one and re-creating it with the right
external net.
The deletion was automatically creating a rubber between it's two
Contact anchors. And we there is no way to get rid of it (other than
also removing the Contacts).
1. They represent an exact area where no metal should be put, and that area
has been computed by the standard cell abstractor and *do not* need to be
expanded. This is the forbidden area, period!
2. They match the shapes of the components inside the standard cell (say an
horizontal segment). In that case, the blockage *must be expanded* by the minimal
spacing rules as any fixed wiring already present.
It is not clear to me what is the accepted norm. This commit stays on semantic [1].
The semantic is implemented in PowerRailsPlanes::Rail::doLayout().
* Change: In cumulus.block.configuration and cumulus.block.htree, two new
configuration parameters allow to specify the offset of the horizontal
branch of the H-Tree manually:
cfg.spares.htreeRootOffset (first level of the tree)
cfg.spares.htreeOffset (subsequent levels)
The offset is given in number of tracks.
* New: In helpers.overlay.CfgDefault, new class that can be used to give
a default value to a cached configuration parameter. The default
value will be used as a last ditch fallback and used *only if* no
default value can be fetched from the C++ database (disk).
* New: In LefImport, add setGdsForeignDirectory() to point out from where
to load the extra GDS file in case a FOREIGN directory is present
in MACRO.
Also add support for merging the supply nets. It may happens that
the supply nets have different names in the GDS ("vdd!") and LEF files
("pvdd"), in that case, the LEF name supersede the GDS one.
The GDS file will be loaded *first* then completed by the LEF contents.
Blockage in the GDS file are *not* loaded.
* Change: In GdsParser, perform an early recognition of supply nets. For now
it's hardwired to names starting by "vdd" and "gnd", but should be
parametrized in the future.
Needed for the LefImport to merge, if needed, the power supplies.
In GdsStream::xyToComponent(), skip the blockage if required.
Formerly we were using Placement::Area::TrackAvoid() to shift cells terminals
out of the way of the reserved vertical track. With double height cells,
this is coming more complex and due to heavy tracks uses in some cells,
the shift required may becomes too great. Instead, we place filler cells
just underneath the reserved track to prevent their usage. This is a
supplemental constraint on the router, but the new version manage it
correctly.
* New: In cumulus/block.spares.Spares.trackAvoid() to place filler cells
under a given vertical area.
Jean-Paul Chaput
Rob Taylor
Robert Taylor
Gabriel Gouvine