* The Hurricane python module was not compiled at all. The name of
Python module wrappers is a bit inconsistent:
isobar --> Hurricane
crlcore --> CRL
anabatic --> Anabatic
katana --> Katana
* Use "py_mod_deps" and not only "py_deps" so the __PYTHON_MODULE__
flag is used for py.extension_module().
* In cumulus, the "cumulus" directory is not used for the installation
in site-packages/coriolis/.
* In designflow/pnr.py, temporarily disable Tramontana & Tutorial,
until they are ported to meson.
In CoreToChip, the "iolib" I/O pad library an alternative to the "cmos"
one. "cmos" uses the pxlib library while iolib uses a symbolic abstract
version of the C4M (real) I/O pad.
The initialization is a bit split as the "cmos" library are part of
Alliance, while "iolib" is in alliance-check-toolkit. So "iolib" is
added at designflow.technos.setupCMOS().
Setup additional configuration parameter directly in:
core2chip.niolib.CoreToChip.__init__().
* Bug: In CRL/technos.node180.gf180mcu_c4m.iolib.py, remove the VDD and
VSS ring terminals in the pad as only *some* of the have it.
Assume that it is a bug from GF. The power rail will still be ok
as it connect by abutment (with the filler & other I/O pads).
* New: In cumulus.plugins.block.configuration.py, added support for
iterable I/O pad specifications in ioPads argument.
* New: In cumulus.plugins.core2chip.core2chip.py, add support for
any number of control signals on I/O pads. Not fully implemented
yet, as we only allow to hard-wire them either to one or zero.
Raise an error if _connect() fails to find a master net, so
we don't fail strangely later...
* New: In designflow.surelog, support for the Synlig Surelog/UHDM plugin
for Yosys.
* Fix: In designflow.svase, remove the transient file "slang-args.txt".
* Change: In designflow.yosys, remove the direct SystemVerilog support
that is delegated to Surelog and just load the resulting UHDM.
Merge with yosysnp and automatically detect if we can load the
Python plugin or go through a script.
* New: In designflow.yosys, add support to load SystemVerilog with the
synlig plugin (CHIPS Alliance).
Integrate back the "non-Python" version of the task. Now switch
automatically between Python & Non-Python based on the availability
of the plugin. Also select between "yosys" & "yowasp-yosys".
* Change: In svase & sv2v, suppress the requirement of the *first*
dependency file to be used as the default target. Now use the
"top module" argument.
* New: In LefImport::LefParser, add support for LEF Polygons that are
translated into Hurricane Rectilinears.
* Change: In LefImport::setMergeLibrary(), the default behavior for the
LEF parser is to create a new separate library under LEF/<lib_name>
for each file. But if the various cells are put each one in it's own
cell, this is suitable. So we can now set a library beforehand into
which they will be all put.
* New: in CRL/technos.node180.gf180mcu, configuration files for the
GF180MCU open PDK.
* New: in cumulus/designflow.technos, added a setupGF180MCU_GF() to
initialize the GF PDK.
* In cumulus.designflow.technos.setupCMOS(): export back the guessed
ALLIANCE_TOP *before* importing technos.symbolic.cmos so it is
used for the CELLS_TOP. This avoid defaulting to /soc/alliance
which does exists only on LIP6 computers...
* New: In cumulus.designflow: add yosysnp to manage Yosys without
Python support enabled.
Add klayout support for running scripts in batch mode.
Add generic system command support.
* Change: In cumulus.designflow.task.TaskFlow, systematically
convert pathes (str) into pathlib.Path in targets and depends.
* New: In cumulus.designflow.clean.Clean, add cleaning by glob.
* Move all Python stuff under a common Python namespace "coriolis".
* Instead of having a series subtrees for each tool, integrate
everything in one common tree. So now, all components can be
located either with an absolute path from "coriolis" or, inside
cross-reference themselves through relatives imports.
* As a consequence, we only need to add ".../site-packages/coriolis/"
to the PYTHONPATH, and not a whole bunch of subdirectories.
And nothing, if installed in-system.
* The tree of free technologies configuration files is also moved
below "coriolis/technos" instead of "/etc".
* Supressed "cumulus" level for the plugins.
* All python modules are rewritten using relative imports except
for the configuration files that uses absolute import as they
can be cloned outside of the tree to serve as templates.
* Change: In boostrap/FindPythonSitePackages, include "/coriolis" in
Python_CORIOLISARCH and Python_CORIOLISLIB.
Provide a Python_SITELIB *without* "/coriolis" appended.
* Change: In cumulus/plugins/__init__.loadPlugins(), must prefix modules
read in the plugins directory by "coriolis.plugins.". No longer need
to add their path to sys.path.
* Change: In crlcore/python/technos/nodeX/*/devices.py, the scripts of
the layouts generators must be prefixed by "coriolis.oroshi.".
* Change: In CRL::System CTOR, no longer add the pathes of the various
plugins to sys.path. Only "site-packages/coriolis/".
* New: In Utilities::Path::toPyModePath(), new method to convert a
filesystem path into a python module path.
Examples:
"coriolis/plugins/block" --> "coriolis.plugins.block".
"coriolis/plugins/rsave.py" --> "coriolis.plugins.rsave".
* Change: In katanaEngine::_runKatanaEngine(), rename the hook script
initHook.py. No longer need to modify sys.path.
* Change: In BoraEngine::_runBoraEngine(), rename the hook script
initHook.py. No longer need to modify sys.path.
* Change: In UnicornGui::_runUnicornInit(), rename the hook script
initHook.py. No longer need to modify sys.path.
* Change: In cumulus.plugins.chip.constants, put the constants
outside __init__.py to avoid a loop at initialization.
Jean-Paul Chaput
Rob Taylor
Gabriel Gouvine