riscv
/
coriolis
mirror of https://gitlab.lip6.fr/vlsi-eda/coriolis.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
3,123 Commits 18 Branches 8 Tags 96 MiB
Commit Graph

5 Commits

Author SHA1 Message Date
Jean-Paul Chaput 9274c21c14 Support for gf180mcu native I/O pads. 
* Bug: In CRL/technos.node180.gf180mcu_c4m.iolib.py, remove the VDD and
    VSS ring terminals in the pad as only *some* of the have it.
    Assume that it is a bug from GF. The power rail will still be ok
    as it connect by abutment (with the filler & other I/O pads).
* New: In cumulus.plugins.block.configuration.py, added support for
    iterable I/O pad specifications in ioPads argument.
* New: In cumulus.plugins.core2chip.core2chip.py, add support for
    any number of control signals on I/O pads. Not fully implemented
    yet, as we only allow to hard-wire them either to one or zero.
      Raise an error if _connect() fails to find a master net, so
    we don't fail strangely later...
 2023-09-25 23:50:20 +02:00
Jean-Paul Chaput ef57ed9da1 Add support for GF180MCU, borrowed from Chips4Makers. 
Original source:
    https://gitlab.com/Chips4Makers/c4m-pdk-gf180mcu.git
Duplicated because I needed to do some patches and combine it with
the vendor I/O pads.
 2023-08-31 16:14:08 +02:00
Jean-Paul Chaput 3243b12abb Try VH topologies for G180MCU. Not working either... 2023-07-03 20:02:33 +02:00
Jean-Paul Chaput 007677353f Using the right cell gauge name in GF180MCU techn o file. 2023-06-25 15:29:35 +02:00
Jean-Paul Chaput 72b906cb68 Forgor configuartion files for GF180MCU. 2023-06-22 17:38:03 +02:00