Commit Graph

2301 Commits

Author SHA1 Message Date
Jean-Paul Chaput f9ea7509df Bug fix, correctly transmit the editor when processing sub-block. 2020-08-06 15:05:25 +02:00
Jean-Paul Chaput 7777d03f3a Correct too rigid topology in NetBuilderHV::_do_1G_xM1_1PinM2 (E/W).
* Change: In Anabatic::NetBuilderHV::_do_1G_xM1_1PinM2(), the M2 pin
    (horizonal) was directly aligned with the outgoing global through
    a H-Tee. This was too rigid. Now it can be misaligned.
2020-08-06 15:04:45 +02:00
Jean-Paul Chaput 140d6f20dc Increase the "reserve" length when moving up long wires (ARM run-17).
* New: In Katana::Manipulator::moveUp(), if the length of the wire is
    greater than 60 pitchs, increase the reserve from 0.5 track to
    1.0 track. This is to left more free tracks when lots of very
    long segments are moved up. Make the run 17 of the ARM test bench
    pass.
2020-08-06 15:04:18 +02:00
Jean-Paul Chaput 748289ad7e Correct context for error message in EtesianEngine::setDefaultAb(). 2020-08-05 01:29:37 +02:00
Jean-Paul Chaput 85d7714910 Solve algorithmic execution time of Anabatic layer assignement.
* Change: In AnabaticEngine::_desaturate(), now use a STL priority
    queue built upon a vector with duplicates of the GCell keys.
      Much much more faster than the previous set with a custom
    sorting key over the GCell. Insertion & removal where getting
    a lot of time. Now it's down to less than a minutes, even for
    big designs.
* Change; In Anabatic::GCells, add the ability to clone the GCell
    key, to use it independently in GCells sorting containers.
      This way the cloned value do not change when the GCell is
    updated. Keep track of the latest (most up to date) cloned
    key.
2020-08-05 01:27:26 +02:00
Jean-Paul Chaput 78b7e683e5 Add a context manager to helpers.overlay.CfgCache.
* New: In CRL/helpers.overlay.CfgCache, add support for context manager,
    so we can progressively remove the use of Configuration. One class
    to use in all contexts (immedaite setting or storing a set of
    Cfg parameters).
2020-08-05 01:26:16 +02:00
Jean-Paul Chaput 5027d5d5ef Bug in error message in AutoContact::getLentgh(). 2020-08-05 01:25:12 +02:00
Jean-Paul Chaput e3515ab900 Don't skip fixed instances in Etesian, stupid!
* Bug: In Etesian::toColoquinte(), inadvertently stopped taking into
    account fixed instances... Compute correctly the number of
    instances to place (all instances minus fixed ones..).
2020-08-03 21:58:38 +02:00
Jean-Paul Chaput 79c5f4db58 Already placed blocks must be flagged as FIXED instead of PLACED.
* Bug: In cumulus/plugins/block/block.py, when a block is found to have
    a layout, that is, is already placed & routed, it's instances must
    be flagged as FIXED instead or PLACED so Etesian will really sees
    them as unmovable and don't account them to be placed.
2020-08-03 19:43:03 +02:00
Jean-Paul Chaput 63854d80c1 Just skip placement when there is no instances to place.
* New: In EtesianEngine::toColoquinte(), fixed blocks must not be
    accounted as instances to be placed.
      When, there is no instances to place, just issue an error message
    and return.
2020-08-03 19:39:09 +02:00
Jean-Paul Chaput ea38329de1 * Bug: In CellCollection::Cell_HyperNetRootNetOccurrences::progress(),
skip Nets that are inside Terminal Netlist master cells. Was done
    ine the locator constructor but forgotten in the progress().
2020-08-03 19:35:21 +02:00
Jean-Paul Chaput 86b184dd1e Bug fix: Bad topology in NetBuilderHV::_do_2G_xM1_1PinM2() again.
* Bug: In Anabatic::NetBuilderHV::_do_2G_xM1_1PinM2(), in the case of a
    bend of global wires, the topology was faulty. Too rigid topology,
    the global wire was forcibly aligned on the external Pin.
2020-08-03 19:28:16 +02:00
Jean-Paul Chaput c63827681a Remove forgotten debug message in KatanaEngine::annotateGlobalGraph(). 2020-08-02 23:02:08 +02:00
Jean-Paul Chaput 6210a08e99 Forgotten some pages of the generated documentation. 2020-08-02 18:22:28 +02:00
Jean-Paul Chaput 3b700baec0 Be more Python3 compliant and replace "beta" menu by "alpha". 2020-08-02 18:20:27 +02:00
Jean-Paul Chaput 835e7264fe New: Cumulus Stats plugin, for trans-hierarchical statistics. 2020-08-02 18:19:05 +02:00
Jean-Paul Chaput 4d1acc35ab New: Reimplementation of the Cumulus Block plugin (in alpha). 2020-08-02 18:18:40 +02:00
Jean-Paul Chaput f211cae69a New: Parameters hTrackReservedMin in Katana.
* New: In Katana::Configuration, two new parameters hTrackReservedMin
   and same for V. Forced decrease of all edges capacities, to use
   when the global router is too optimistic...
2020-08-02 18:16:21 +02:00
Jean-Paul Chaput d6b90a70ab Enable Etesian to compute AB of fixed width.
* New: In EtesianEngine::setDefaultAb(), add computation of AB when
    using fixed width (fixed height) was already available.
      Add attribute management for the fixed width along with a
    Python export.
2020-08-02 18:15:15 +02:00
Jean-Paul Chaput 5498ad9ecb Bug fix: Never slacken a segment from a Pin.
* New: In Anabatic::AutoContactTerminal, new method "isOnPin()" to
    know if the terminal contact is on a Pin. Introduced in base
    class.
* Bug: In Anabatic::AutoHorizontal::_canSlacken() & AutoVertical,
    forbid slackening from a Pin. As Pin are all on the side of the
    cell (aligneds) and the perpandicular segment will be locked on
    the Pin, it generates intractable overlaps for the router.
2020-08-02 18:13:47 +02:00
Jean-Paul Chaput be2f9f8a45 Bug fix: Always select the Pin as best RoutingPad component.
* Bug: In Anabatic::Configuration::selectRpComponent(), always select
    the Pin as the best component. It is mandatory for a block that
    we pick up the terminal at the periphery and not one deep inside
    the block.
* Bug: In Hurricane::RoutingPad::setOnBestcomponent(), same rule as
    in Anabatic, if there is any, the Pin must always be the best
    RoutingPad component.
2020-08-02 18:12:52 +02:00
Jean-Paul Chaput a971f6f91b Bug fix: Bad topology in NetBuilderHV::_do_2G_xM1_1PinM2().
* Bug: In Anabatic::NetBuilderHV::_do_2G_xM1_1PinM2(), in the case of a
    bend of global wires, the topology was faulty. Badly connected HTees.
2020-08-02 18:11:39 +02:00
Jean-Paul Chaput de6308d8d4 Bug fix: ApDriver was not saving "blockageX" layers.
* Bug: In CRL/ApDriver/toMbkLayer(), add translation entries for
    converting "real" blockage layers. So they don't get ignoreds...
2020-08-02 18:09:46 +02:00
Jean-Paul Chaput 1e3788d93e New Python class helpers.overlay.CfgCache.
* New: In CRL/helpers/overlay.py, CfgCache class to hold a set of
    configuration parameters and apply it on demand. It has a
    different behavior than Configuration.
2020-08-02 18:09:02 +02:00
Jean-Paul Chaput 3996a8e15d Change: In Hurricane::CellViewer, rename "beta" menu to "alpha". 2020-08-02 18:08:14 +02:00
Jean-Paul Chaput 0745498505 Export the Pin name and direction to the Python interface.
* New: In Hurricane::PyPin, export ::getName() and ::getPlacementStatus().
2020-08-02 18:07:27 +02:00
Jean-Paul Chaput 134044ee99 Bad indentation in oroshi/dtr.py (from latest merge). 2020-07-22 17:26:28 +02:00
Marie-Minerve Louërat 7ae37a2ac3 Merge branch 'devel' of gitlab.lip6.fr:vlsi-eda/coriolis into devel
Conflicts:
	oroshi/python/dtr.py
2020-07-22 15:05:00 +02:00
Marie-Minerve Louërat be0255c27b Merge branch 'devel' of gitlab.lip6.fr:vlsi-eda/coriolis into devel
Conflicts:
	oroshi/python/dtr.py
2020-07-22 15:00:19 +02:00
Jean-Paul Chaput 17ecfd823b Enhanced techno rule support. Inspector support bug fix.
* Bug: In Hurricane/Commons.h, modify the getRecord<>() templates so
    that for both vector<Element> and vector<Element*>, the individual
    record created for each element are donne with pointers. That is,
    for the vector<Element> case, we take a pointer.
      As a general policy, except for the POD types, always use pointers
    or references to data in the records/inspector. Never uses values
    that can call the copy constructor.
      Suppress INSPECTOR_PV_SUPPORT() macro, keep only
    INSPECTOR_PR_SUPPORT().
      Provide value support only for getString<>() template.
      This value & copy constructor problem was causing a crash when
    trying to inspect Hurricane::AnalogCellExtension.
* New: In Hurricane::Technology, change the API of the PhysicalRule,
    now we can only create/get PhysicalRule, but setting the value of
    the rule itself must be done on the rule.
      Enhance PhysicalRule to provide for stepped rules, non isotropic
    and ratio rules.
      Merge TwoLayersPhysicalrule in PhysicalRule, much simpler to
    suppress the management of derived classes. That means that we
    loose a little memory as some fields are mutually exclusive.
    Not a problem considering that there will not be so many of thoses
    objects.
* New: In CRL/helpers.analogtechno.py, enhanced DTR support for rules
    like:
      ('minSpacing'  , 'metal1', ((0.4,20.0), (0.8,1000.0)), Length, 'REF.1')
      ('minEnclosure', 'metal1', 'cut1', (0.2,0.3)         , Length, 'REF.2')
      ('minDensity'  , 'metal1', 0.30                      , Unit  , 'REF.3')
      The DTR parser has been updated, but not the oroshi.dtr Rule
    cache for analog components. Given a rule name, the value used
    will be the horizontal one of the first step.
* Change: In hurricane/doc/hurricane, re-generate the documentation
    with updated support for Technology & PhysicalRule.
2020-07-21 11:22:04 +02:00
Jean-Paul Chaput 34c1795630 Support for long in CRL/overlay.Configuration.__setattr__(). 2020-07-14 19:55:20 +02:00
Jean-Paul Chaput 960e0cda18 In CRL::NamingScheme::vlogTovhdl(), remove '%' invalid VHDL character. 2020-07-14 19:53:34 +02:00
Jean-Paul Chaput 8ce2a7e318 In Etesian, do not reset the placement if we are using a sub-block.
* Bug: In EtesianEngine::place(), reset the placement *only* if we are
    *not* placing a sub-block *and* the top cell abutment box is empty.
* Bug: In EtesianEngine::place(), set the instance placement status of
    all intermediate instances to PLACED, so the AP driver will save
    them (we were having partially saved layout when using hierarchical
    designs).
* Bug: In EtesianEngine::resetPlacement(), reset the PLACED flag and
    the abutment box on the top cell or sub-block to be placed.
2020-07-14 19:51:01 +02:00
Jean-Paul Chaput e4041d5e26 Improved Hurricane/Python database reset.
* Change: In CRL/helpers/__init__.py, to ensure a complete restart of
    the database the __init__.py must be called again, but it's not the
    case with reload() (see Python doc). So helpers.resetCoriolis()
    must explicitly removes the Coriolis related Python modules from
    sys.modules (calling "del sys.modules[moduleName]").
      That list of Coriolis Python modules is built by calling
    helpers.tagConfModules(), it will tag all modules added to
    sys.modules since startup. It will remove (much) more than
    Coriolis modules, but that should be ok.
* Change: In CRL/etc/{node*,symbolic}/TECH/__init__.py, add a call to
    helpers.tagConfModules() for the techno modules to be erased on
    reset.
2020-07-14 19:49:54 +02:00
Marie-Minerve Louërat e7bf8022f7 Ajout de règles 2020-07-09 17:05:57 +02:00
Jean-Paul Chaput 010fc79f4f Added rule minWidth_nWell to oroshi rule loader. 2020-06-30 14:54:42 +02:00
Jean-Paul Chaput 441cb71475 * New: In Anabatic::NetBuilder, to tackle once and for all the GCell
configurations for Libre-SOC manage up to 9 METAL1 terminals in
    1G to 4G configurations.
2020-06-30 10:00:29 +02:00
Jean-Paul Chaput 424b66e671 Added new GCell configurations to handle Libre-SOC test_issuer.
* New: In Anabatic::NetBuilder, some GCells configurations of Libre-SOC
    "test_issuer" (soclayout/experiments9) did have more METAL1 terminals
    than was though possible. Just added more entries in the connexity
    table for bigger numbers of METAL1. No new configuration was added,
    used the already existing ones.
2020-06-29 13:02:27 +02:00
Jean-Paul Chaput f3dd4bcd31 Fixes cumulus recursive save plugin.
* Bug: In cumulus/plugins/rsave.py, use "Cell.isTerminalNetlist()"
    instead of "Cell.isTerminal()" to find the hierarchical stop
    points.
      If the root cell to be saved is itself a *terminal netlist*
    one, save it anyway. The top level *must* be saved regardless to
    it's status.
2020-06-26 17:13:52 +02:00
Jean-Paul Chaput b48f9b40b8 Fixes bad VHDL port map assignment for vectors in VST driver.
* Bug: In CRL/Vhdl::VectorPortMap::toVhdlPortMap(), two problems:
    1. Bad condition for the use of VstUseConcat. Must be used *only*
       when there is more than *one* mapped name.
    2. Missing case, when there is exactly *one* mapped name, that
       means that we have one full width vector to vector assignement.
       There may be another weakness here, for the portmap we assumes
       that both vector are mapped in the *same* direction (which is
       "downto" by our convention).
    3. In the "bit by bit mapping case" (every bits of the vector are
       differents bits), use the "signal + bit index" name instead of
       juste the signal name (i.e. full width).
    Solves the Libre-SOC/soclayout/experiment6/fpmul64 problem, now
    we can avoid the YOSYS_FLATTEN.
2020-06-26 17:13:18 +02:00
Jean-Paul Chaput b23f620c5d The VST driver may suppress linkage type.
* Change: In Vhdl:::Signal::toVhdlPort(), in Alliance VST signal with
    undefined directions are typed "linkage". This may not be compatible
    with vasy, so allow to replace them by "in".
* New: In CRL::Catalog::State, add a new flag VstNoLinkage to tell if
   the VST driver should not use the "linkage" type.
* Change: In Vhdl::Entity, add a VstNoLinkage flag to disable the use
    of the "linkage" type.
2020-06-24 23:27:21 +02:00
Jean-Paul Chaput 1ccb9c340f Add setters for space margin and aspect ratio in Etesian.
* Change: In EtesianEngine, add setters for space margin and aspect ratio.
    Export them in Python.
2020-06-16 21:39:10 +02:00
Jean-Paul Chaput b0a3bb33af Add early error detection for misaligned Pins.
* Change: In AnabaticEngine::checkPlacement(), add a check on all the
    external pins for preferred layer direction and routing grid
    alignement.
2020-06-16 21:38:21 +02:00
Jean-Paul Chaput 235a9eecea Adjustements to the ExceptionWidget behavior.
* Change: In Hurricane::ExceptionWidget,
    - Use a QTextLabel instead of a QLabel, make it "look like" a QLabel.
    - Always display using text mode. Not HTML (to preserve indentation).
    - Make the text of the error message selectable.
    - Make it resizable.
2020-06-16 21:37:18 +02:00
Jean-Paul Chaput 9c082230b5 Add forgotten asDouble() method to the Parameter interface.
* New: In vlsisapd/PyConfiguration, add asDouble() to the Parameter
    Python wrapper.
* New: In CRLCore/helpers/overlay, add support for float parameters
    in configuratuon.
2020-06-16 21:33:33 +02:00
Jean-Paul Chaput 09192ba084 Bug fix, check for unconnected signals in CRL::VectorPortMap::toVhdlportMap().
* Bug: In CRL::VectorPortmap::toVhdlPortMap(), unconnected bits where
    correctly checkeds for multi-bits vectors (both ordered and holed),
    but not for mono-bits connections (ONE bit of a vector).
2020-06-09 14:08:08 +02:00
Jean-Paul Chaput 5d891b2cd8 The VST driver is now allowed to preserve the case of identifiers.
* New: In CRL::NamingScheme, add a flag VstNoLowerCase, and its
    management it in the Verilog to VHDL converter.
* Change: In CRL::BlifParser::Model::toVhdlModels(), disable the
    lowercasing of identifiers. We shouldn't apply Alliance VHDL
    subset constraits when reading blif files. So we will see
    uppercase identifiers in Coriolis.
* Change: In CRL::VstParser, no longer lowercase identifiers that
    are *not* VHDL keywords. Uppercases are legals in VHDL...
* New: In CRL::Catalog::State, add a new flag VstNoLowerCase to
    tell if the VST driver should keep the uppercases.
* Change: In CRL::VhdlEntity, add a VstNolowerCase flag to disable
    the lowercasing.
* Change: In CRL::vstDriver, lower case the file name if needed.
    remove the previously opened filename if it differs from the
    lowercased one.
* Change: In UnicornGui CTOR, disable VHDL enforcement for the
    Blif parser.
2020-06-08 13:34:25 +02:00
Jean-Paul Chaput f91fc4f927 Add experimental matrix placer into cumulus.
* In cumulus.plugins.matrixplacer.py, BETA plugins for getting back
    matrix-like netlists placement. This plugin is configured *ONLY*
    for Libre-SOC FU-FU matrix 30x30.
2020-06-06 12:16:51 +02:00
Jean-Paul Chaput f2a60768ca Export Entity::getId() to the Python interface. 2020-06-06 12:13:57 +02:00
Jean-Paul Chaput 7b1dab7742 Generate only one/zero cell in Blif parser.
* Change: In CRL::BlifParser, formerly, a zero/one cell was added for
    each vss/vdd direct connection, generating a huge flock of cells.
    Now only generate one per netlist.
      It can be discussed whether to old behavior is more desirable,
    it is a compromise between wire and area.
2020-06-06 12:13:29 +02:00