* Bug: In CRL Core, in VectorPortMap::VhdlPortMap(), if the connection
was made to *non-contiguous* bits of an otherwise *contiguous* vector,
it was using a span instead of the separate bits. Now check that
bits are contiguous (delta: +1/-1) and the delta do not change of
sign.
* Change: In Etesian & Kite, the Python interface function ::setViewer()
was checking that the argument was indeed a CellViewer, but in text
mode it is None. Now, silently ignore the argument if it cannot be
converted into CellViewer.
* New: In Hurricane, in Collection add simple STL iterator support.
So now the C++11 "for" instruction can be used instead of the
in-house "forEach".
Example:
forEach ( Component*, icomponent, net->getComponents() ) {
cout << (*icomponent) << endl;
}
Become:
for ( Component icomponent : net->getComponents() ) {
cout << icomponent << endl;
}
* Change: In bootstrap, in FindLEFDEF.cmake, adds my personal path where
the LEF/DEF libraries are to be found (~jpc/oa/lefdef/5.7-s038/).
* Change: In CRL Core, in LEF/DEF exporters, use the default routing
gauge and cell gauge, instead of systematically requiring "sxlib".
IMPORTANT: In order to build a *shared* library including the
*static* LEF/DEF libraries, those libraries, even if static, must
be build with the "-fPIC" flag (otherwise the compiler complains).
I have done so on my 64 bit build of LEF/DEF, but it's a completly
*local* patch. You may have to do it manually on your installations.
* Change: In CRL Core, replace duplicated libraries, even when performing
a Append/Prepend operation. Also correct a bug in library name
uniquification, event if it's no used. The policy in cas of duplicate
libraries is not completly clear for me, still.
* New: In Hurricane, in Graphics, add a new static method ::isHighDpi()
which returns true if the DPI is greater than 192. A "normal" screen
is typically 96dpi, we sets the trigger at twice that value.
Then in all the widgets with size settings, we uses that method to
select the more appropriate size.
* Bug: In Hurricane, in PyHurricane.h the macro HCATCH was not catching
standard STL exceptions. This was the source of the cryptic message:
"Fatal Python error: Py_EndInterpreter: thread still has a frame"
The Python interpreter was interrupted uncleanly bypassing it's own
exceptions mechanism.
In PyViewer, the Viewer *do not* inherit from a base class (in the
Python export).
* New: In Hurricane, in DbU, compute maximum values (in double) for
grid, lambda & physical (in meter) so now the DbU::toGrid(),
DbU::toLambda() & DbU::toPhysical() methods can check for out of
bound values, and throw an exception.
* Change: In Hurricane, ExceptionWidget::catchAllWrapper() now returns
a boolean, set to <true> if an exception has been catched. Allow
callers to interrupt themselves if a problem has occured.
* Bug: In Kite & Etesian, in the Python wrapper, send a Python exception
if catchAllwrapper() did return true, instead of continuing...
* Change: In Kite & Etesian, adds a setViewer() method (exported in Python)
to use the graphical ExceptionWidget when in graphic mode.
* Bug: In Cumulus, in PadsCorona.py the check for the core vs. chip size
was not returning False when invalid.
* New: In CRL Core, in Vst driver, add a support IEEE VHDL. Inactive for
now as I don't see clearly the policy for selecting it or not.
Remove the code of the old Vst driver.
In Blif parser, check for non-existent models (incomplete or
corrupted Blif file). Found by G. Gouvine.
* New: Added extras file for IDE-like support under Emacs.
* New: In CRL Core, in VstParser, support IEEE VHDL, with tokens
<library> and <use>. If "use IEEE.std_logic_1164.ALL" is present
the file will be considered to be IEEE compliant.
To be precise, the parser now support any mix between Alliance
and IEEE VHDL. So you can have both <std_logic> and <wor_bit>
in the same file, but it is unclean to do that.
The two extensions ".vhd" & ".vhdl" are supported.
The drivers still always creates Alliance VHDL.
* New: In CRL Core, created a LibraryManager widget. It provides a
composite information based on what is present, for each
Alliance library:
1. - A Cell in memory, without Catalog::State.
2. - A Catalog::State, with or whithout the Cell in memory.
3. - The files of the Cell in the librariy's directory.
4. - A file with a format referenced for one of the importers.
File type recognition is based *only* on the file extension,
so it may easily confused. Be careful about what you put in
the library's directory.
One of the big limitation is that it will not display Hurricane
libraries that do not have the AllianceLibrary extension.
This widget is put in a separate library <libmanager>, included
in the default CRLCORE_LIBRARIES.
* Change: In CRL Core, in State (through the loader), now sets the
InMemory flag (event if nobody uses it yet...). Display it in
the state _getString().
In AllianceFramework, new getAllianceLibraries() method.
In CatalogExtension, make the static method "get()" publicly
accessible, for sometimes we want the whole State.
* Bug: In vlsisapd, in Path, the pathcache was not rebuild when it
should, leading to incorrect results.
* New: In vlsisapd, in Path, added a listdir() method to access the
contents of a directory and a stat() method to poll the status
of a file/directory.
Rename the ".string()" method in ".toString()" to avoid
tricky name resolution with std::string, refactor in all the
other tools.
* Change: In Hurricane, in Controller, no longer oversize the fonts
of the table's headers.
* New: In Unicorn, in UnicornGui, integrate LibraryManager.
* Error messages are more explicit in Ap and Blif parsers
* Warns when not using tie cells
* New layer synonym in ApParser for easier format conversion
* Blif import is now on top
* Bug: In Hurricane, in NetAlias, bad Record construction of the _next
field.
* New: In CRL Core, in VstDriver complete replacement of the old Vst
driver. Needed cleaner architecture to manage correctly files
importeds through the Blif parser, which are Verilog like.
It is build as an extension trough property and is not kept
in sync with the Cell. So it's use should be transient only.
* Change: In CRL Core, in NamingScheme forgot to change '.' (dot)
forbidden character into '_'.
* Change: In Cumulus, in the RSave plugins, remove the VHDL extensions
after saving.
* New: In Hurricane, In NetAlias & Net, add an AliasList collection to
iterate over all the aliases names (this *not* include the main
net name).
* New: In Hurricane, In Cell, Instance & Net add support for cloning and
uniquification (update documentation).
All Cells that are uniquified from a given model are kept in an
Uniquify relation. This relation allows to get all the clones and
generate unique clone names by adding a "_uXX" suffix.
* Bug: In Hurricane, the Cell::_isFlattenLeaf attribute was not initialized
in the constructor.
* Change: In CRL Core, in AllianceFramework::getCell(), no longer destroy
a partially loaded Cell in case of parser failure, let the incomplete
Cell be.
* New: In CRL Core, in ApParser, if all the instances are placed, sets the
Cell::Placed flag.
* Change: In CRL Core, in BlifParser, complete rewrite of the parser.
Not so good an idea afterwards...
* New: In Etesian, uniquify the design before placing.
* Change: In Kite, display the list of unrouted wired after all other
statistics.
* New: In Hurricane, In Cell, add Placed and Routed flags to know the
state of the Cell.
* Change: In CRL Core, In ApDriver, do not save the RoutingPads as
external connectors if the design is *not* routed (create
conflics on reload with the newly generated RoutingPads).
* Change: In Etesian, set the Placed flag on the Cell.
* Change: In Kite, set the Routed flag on the Cell.
* Change: In Cumulus, in RSavePluginAll, save the layout only if it
has a bounding box.
* New: In Hurricane, In Net & Cell, support for Net aliases names.
Use a structure based on a simple ring of NetAliasHook. The Net
holds a global map, sorted by names of all the aliases of all Nets.
Elements NetAliasesHook of the map are slaves of ring whose master
is an attribute of the Net (it is *not* in the map, as the primary
name of the Net).
In case of merge, the aliases of both Nets are merged and the
name of the merged one become an alias.
The Cell::getNet() looks in both the Net map and the aliases to
find a Net by name.
* Bug: In CRL Core, in coriolisInit.py, reoder the loading of the
configuration files so the real technology is read as early as
possible to set up the <gridsPerLambda> factor before any lambda
is actually computed...
* Bug: In CRL Core, in AcmSigda, do not try to fed the file when it
has failed to be opened. Throw a clean exception instead.
* New: In CRL Core, in Toolbox, add a NamingScheme object to convert
a design into VHDL compliant names (mainly from Blif/Verilog).
This is extensible in any case.
* New: In CRL Core, in BlifParser, slightly more informative warning
messages. Align the loading progress information on the other
parsers.
Add a capability to select which component of the design will
be returned, if there are more than one. Use the "." as separator.
For exemple you can request "Processor.Alu", which will load
the "Alu" component from the design in "Processor.blif".
To be able to save a Blif loaded design, systematically convert
all the name for VHDL compliance, as it is the format used by
the Coriolis native files (vst).
Export the Blif parser to the Python interface.
* New: In Kite, In NegociateWindow, add a counter of the number of
remaining events. Gives an idea of the ETA...
* New: In Unicorn, in cgt.by, add an option to load a Blif design from
the command line.
* New: In Cumulus, new RSave plugin to save both netlist & layout.
Partly redundant with the previous one. Have to better organize
that later.
* Change: In CRL Core, simplify the loading sequence. The technology,
both symbolic and real is now loaded directly from coriolisInit.py
and not through the Alliance loader. This was a leftover from the
time configuration was in XML. Remove others traces of XML loading.
Remove SYMB_TECHNO_NAME, REAL_TECHNO_NAME & DISPLAY from the Alliance
environement, as they was no longer used.
Note that technology *still* need to be loader *after* Alliance
framework has been initialized.
Gauge information is moved from <alliance.conf> to <kite.conf>.
* Bug: In Coloquinte, in optimization_subproblems.cxx static variables
must not be inlined. Generate a problem when linking in debug mode
(seems the symbol gets optimised out).
* Bug: In Katabatic, in Grid::getGCell(), when the coordinate is *outside*
the area, do not try to find a GCell, directly return NULL.
* New: In Unicorn, create a generic command launcher named "coriolis" which
automatically take cares of all environement setup, then run a command
by default, it's <cgt>, but it can be anything. For example: <zsh>.
* New: In CRL Core, remove obsoleted XML files, no longer needed by
Chams. Add stub for technologies CMOS065 (ST) and C35B4, aka
AMS 035.
* Bug: In Knik, update the path where to find the FLUTE lookup tables.
(from 2.4 to 3.1).
* New: In Hurricane, In CellWidget, add methods to emit CellPreModificated
and CellPostModificated Qt signals (from non-Qt aware objects).
* New: In Unicorn, In ImportCell, parsers are now dynamically hooked
in the importer, allowing third party application (i.e. Chams) to
add their own. See the ImportCell::addImporter() method.
* Bug: In Unicorn, in FindUNICORN.cmake, seems to be unable to detect
the UnicornGui.h. Not a blocking problem because the include dir
is shared with other tools correctly detected. But still...
* New: In VLSISAPD, in Configuration, add a new priority level UserFile
to distinguish between the system configuration files and the user's
configuration files (which take precedence).
* New: In Hurricane, in Script (Python), improve the API to be able
to support Chams (and remove the duplicate capability from it).
Add separate functions to perform the initialize/run(s)/finalize
cycle step by step.
* Change: In CRL Core, rename real technology <hcmos9> to <hcmos9gp>,
it's offcial name from CMP/ST. This is the 130nm.
Move the reading of the symbolic & real technologies names from
coriolisInit.py to helpers.__init__.py, to be shared with
chamsInit.py.
To avoid a clash of names inside of helpers, the two variables
of techno.py are renamed "symbolicTechnology" and "realTechnology".
Move python init system from crlcore/src/crlcore to crlcore/python.
* New: In CRL Core, In Utilities, add site-packages/pharos to the
PYTHONPATH.
* Change: In Kite, move python init system from kite/src/init to
kite/python.
* Bug: In CRL Core, in Ispd05Bookshelf, as the pitch is already expressed
in DbU, do not apply DbU::toLambda() in any expression where it is used.
* Change: In Etesian, In AddFeeds, do not try insert feeds if there is no
cell feed avalaible.
* Change: In Bootstrap & ccb, the coloquinte project is renamed into
"importeds", it will be the home of all the externally
devellopped softwares that are needed to build Coriolis.
Add explicit support for Fedora ("Linux.fc") and uses
site-packages, as everybody else.
* New: In CRL Core, in etc/, adds the configuration files for Etesian.
* New: In Etesian, activate the Configuration object. Now uses it's
own configuration variables instead of borrowing those of
Nimbus & Mauka.
* Change: In Documentation, updated User's Guide to present Etesian
as the placer, instead of Mauka.
* Change: In Cumulus, slight change in ClokTreePlugin and ChipPlugin
to match the new Etesian/Python interface.
* New: In Bootstrap, in ccb.py, check if cmake is installed and issue
a warning, if not.
* New: In Hurricane, added Cell::getDeepNet() to search for a deepnet
given a path and a leaf net. This method is slow and must not be
used too often. Introduced for Kite::BuildPowerRails().
* Change: In CRL Core, in cmos/alliance.conf, modify the clock name
pattern to match the sub-clock signals in the datapath operators.
* Bug: In Etesian, do not blindly reset the top cell abutment-box.
Do it only if it's empty, otherwise keep it.
* Bug: In Kite, in buildPowerRails(), in getRootNet() the management
of clock nets was incomplete. The case of unrouted clock nets
that where not connected to the top core clock net, like the
one in the datapath registers was faulty. They were partly
recognized as unrouteds and partly as blockage generating a
routing deadlock: routage impossible due to blockage generated
from itself...
* New: In Stratus1, add a buildModel() utility function to automate
the model generation and allow a call by the model name (string).
* Change: In Unicorn, in cgt.py, display the Alliance environement.
* New: In Hurricane, in DebugSession, add a new method to activate the
trace inconditionally with a certain level.
* New: In Hurricane, in HyperNet, allow copy construction as there is
no reason to disallow it and we need it now.
* New: In Hurricane, in Cell::flattenNets(), add a new option to prevent
the flattening of the clock net(s). For more safety perform the
DeepNet creation *outside* the Collection loop.
* Bug: In Hurricane, in Cell_HyperNetRootNetOccurrences, skip the
DeepNets because they are the result of another flattening operation.
* New: In Isobar, in PyBasicLayer, export C++ method getBlockageLayer().
* New: In Isobar, in PyRoutingGauge, export C++ method getLayerPitch(),
needed by Cumulus plugins.
* New: In Etesian, EtesianEngine::findYSpin() to look for the Y orientation
if some cells are already placed. Typically the buffers of a clock
tree.
Pass the correct orienation to row_compatible_orientation().
Do not try to add feeds in the ISPD05 benchmarks. For now the
benchmarks are detected through their names (unreliable).
* Change: In Knik, in KnikEngine::initGlobalRouting(), allow the clock
to be routed as an ordinary signal when the clock tree is not
used.
* New: In Kite, in BuildPowerRails, management & detection for the
pre-routed clock.
In KiteEngine constructor, early initialization of the blockage
net to avoid later troubles in BuildPowerRails.
* New: In Cumulus, in ChipPlugin, add support for Etesian plus new
configuration parameter 'clockTree.placerEngine' to select between
Mauka and Etesian.
* New: In Cumulus, in BlockCorona, add blockages in the vertical sides
in the vertical layer to prevent the router to use the vertical
tracks in under the prower lines (for example, blockage in M3
with power line M5).
In Cumulus, in ChipConf add attribute to access the blockage net.
* New: In Cumulus, when the clock tree is disabled, do not generate
the last rail around the block (the clock rail).
* Bug: In Cumulus, in ChipConf use the clock pad to guess the clock
signals and *not* the power pad.
Add more meaningful error messages if a pad global signal is
not found (implicit connexion by name).
* Bug: In Cumulus, in ClockTree, compute correctly the cells Y spin,
that is *from the bottom of the cell AB* (not from 'zero').
* Bug: In Bootstrap, in coriolisEnv.py, check if devtoolset-2 is already
active before launching it as a sub-shell.
* Bug: In Isobar, In PyHurricane.h, DBoDestroyAttribute() set the proxy
pointer toward the C++ object to NULL. So when the Python object is
deleted no double-deletion occurs on the C++ object.
Add some more trace information in Python link/dealloc.
* Change: In CRL Core, in cyclop, make CMakeLists.txt automatically
choose the right rule for linking the binary wether we use Qt 4 or
Qt 5. Very irksome problem.
* New: In EtesianEngine::addFeed(), do not take into account instances
that are not placed entirely inside the top cell abutment box (was
causing a core dump).
* Bug: In Katabatic, in GCellQueue, correct a mismatch between a GCell
set and the iterators used upon it.
* Bug: In Mauka, in Row & Surface correct a mismatch between a container
and it's iterator.
* New: In Etesian, updated to work with the latest Coloquinte, patch
contributed by G. Gouvine.
Added EtesianEngine::setDefaultAb() to compute an abutment box if
the Cell is completly unplaced.
* New: In cumulus, in ClockTree, now the placer can be configured to be
either Mauka (slow simulated annealing) or Etesian (fast analytic).
New setting 'clockTree.placerEngine' in plugin settings.
* New: In Bootstrap, in Builder & coriolisEnv.py support for RHEL7/SL7.
The sub-directory name is 'el7_64'.
In qt_setup() add QtSvg to list of Qt5 & Qt4 used libraries.
* New: In Hurricane, In Cell add a placeholder for flags. First use to
store whether the Nets have been transhierarchically flatteneds.
* New: In Hurricane, In NetRoutingState add an Unconnected flag for
more accurate diagnosis.
* New: Hurricane, in CellViewer add an entry menu for stress tests.
The script must be named "stressScript.py" in the cwd.
* Change: In CRL Core, in display.conf add a scaling parameter for the
display threhold of the layer. This way we can adapt to different
standard cells height.
* Change: In CRL Core, in ISPD05 bookshelf loader, use the pitch of the
cell gauge instead of a hard-wired 5.0.
* Change: In Cumulus, in ClockTreePlugin, add support for Etesian placer
and a new configuration parameter to choose between Mauka/Etesian.
* New: In Etesian, support for the latest Coloquinte.
Add feed insertion stage.
* Bug: In Kite, In BuildPowerRails, check that _ck is not NULL before
tring to access it's name...
* Change: In Kite, check if the Cell has it's Nets flattened before
doing it (or not).
* Change: In CRL Core, in VstParserGrammar.yy display in which mode a file
is read. Behavioral, structural or model. Model is the step of reading
the instance's models before truly reading the file.
In addition, a small optimization, when in behavioral mode, parse
the file only once.
* Bug: In CRL Core, in VstParserGrammar.yy & VstParserScanner.ll, accurate
error message positions (file & line numbers).
When generating error message, we cannot pass char* on variables that
will be deallocated by the throw. So generate a string that will be
copied along with the exception. That problems explain numerous
core-dump when encountering syntaxes errors in the file.
* New: In Bootstrap, added support for RHEL7 in ccb.py & coriolisEnv.py.
In coriolisEnv.py, under RHEL6, directly launch a shell under
devtoolset-2 (do not put it in .bashrc).
* Change: All tools, compliance with Clang 3.2.
- Call using namespace std *after* at least one include of std has
been used.
- In Utilities.h define both const and non-cont overload for operator<<
of mstream (this was the true cause of the Banner display problem).
- No longer use defaults arguments in templates, instead create two
separated overloads.
- Put template static attributes allocation outside of namespaces
(this one I'm not sure how to justify).
- Protect by NDEBUG variables that are only needed in assert().
- In PyInterval getUnion() & getIntersection() we where silently
overwriting the "self" object (interval).
- In Mauka, *do no* overload _postCreate() and add an argument, breaks
the virtual function mechanism. Rename it into _maukaPostCreate().
Idem for SubRow().
- In Katabatic::GCell(), invalidate() overload a Go funtion but is
used for different purpose at this level. Rename it invalidateCt()
(invalidate *ConTents*).
- Miscellaneous small cleanup.
* Change: In CRL Core, in coriolisInit.py now read the configuration
files from a ".coriolis2/" directory. This is to avoid too many
dot files in the user's directory. Files have also been renamed:
.coriolis2.conf ==> .coriolis2/settings.conf
.coriolis2_techno.conf ==> .coriolis2/techno.conf
* Change: In Kite, in kiteInit.py follow the same policy as CRL Core
for configuration file.
.coriolis2.kite.py ==> .coriolis2/kite.py
* Change: In Hurricane, the NetRoutingProperty is moved into Hurricane
from Katabatic. Needed for Knik to be able to access thoses
informations.
* Change: In Hurricane, in RoutingPad::setOnBestComponent(), now in
case of identical area, select the component of lowest id.
This should not be needed if the component ordering was fully
deterministic as it should be (will investigate later).
This is to ensure that the choosen component is always the
same, especially between save/load of a global routing.
* Bug: In Katabatic, in AutoContactHTee::updateTopology(), invalidate
the segments only if the topology is valid (no NULL in the
cached segments).
* Bug: In Katabatic, in GCellTopology::construct(), throw an error
if the topology is bad instead of trying to continue (and core
dump later... ).
* Bug: In Kite, in BuildPowerRails, distinguish the name of the master
net in the pad (for vddi, vssi, vdde, vsse, ck, cki & cko) and the
name of the net in the *chip* netlist. Must use the later to make
comparison as they may differs.
* Change: In Knik, in save/load solution, exclude nets that are not
globally routed by Knik. That is which NetRoutingProperty is not
*Automatic*.
* Bug: In Cumulus, in chip.BlockPower take account of the layer
width extention to sligthy shrink the connector thus avoiding a
notch with standart cell in some cases.
* Change: In Cumulus, in chip.ClockTree disable the use of fixed Steiner
trees for the leaf clocks, as it seems overconstrained for the
router. First move was to lower them in M2/M3 (instead of M3/M4)
but that was not sufficent.
* New: In Cumulus, RSavePlugin for recursively saving a physical
hierarchy.
* New: In documentation, first embryo for RDS file. Should have been
in Alliance git, but I prefer to keep newest doc in Coriolis.
* New: In CRL Core, in helpers & alliance.conf, set and read a "PAD"
variable to define the pad model name extension ("px" for "sxlib
and "pxr" for vsxlib, this is provisional).
* New: In CRL Core, in plugin.conf, add parameters to define the name
of used for power & clock supply. We may remove the extention in
the future (to be more coherent with the previous modification).
* New: In Cumulus, in chip.Configuration.GaugeConf._rpAccess(), no
longer place the accessing contact *at the center* of the
RoutingPad. It works under sxlib because buffers & registers all
have same size terminals. But this is not true under vsxlib,
leading to misaligned contacts & wires. Now systematically place
on the slice midlle track (maybe with one pitch above or below).
This is still very weak as we do not check if the terminal
reach were the contact is being put. Has to be strenthened in
the future.
* New: In Cumulus, in chip.Configuration.ChipConf, read the new
clock & power pad parameters.
* Change: In Isobar (and all other Python wrappers), uses PyLong instead
of PyInt for DbU conversions. In PyHurricane argument converter,
automatically check for both PyLong and then PyInt.
* Change: In Cumulus, in chip.PadsCorona, more accurate error message
in case of discrepency in global net connections (i.e. no net
of the same name in instance model and instance model owner.
* Change: In Kite, in BuildPowerRails, when looking up at the pads
model name to find "pck_" or "pvddeck_", do not compare the
extension part. But we still use hard-coded stem pad names,
maybe we shouldn't.
* Bug: In Katabatic, in GCellConfiguration::_do_xG_xM1_xM3(), there
was a loop in the search of the best N/E initial RoutingPad.
* Bug: In Kite, in KiteEngine::protectRoutingPads(), *do not* protect
RoutingPads of fixed nets, they are already through the
BuildPowerRails stage (and it's causing scary overlap warning
messages).
* Bug: In Cumulus, in ClockTree.HTreeNode.addLeaf(), do not create
deep-plug when the core is flat (not sub-modules). All the new
nets are at core level.
* Bug: In Cumulus, in ChipPlugin.PlaceCore.doFloorplan(), ensure
that the core is aligned on the GCell grid (i.e. the slice
grid of the overall chip).
* Bug: In Kite, in GCellTopology::_do_xG_xM1_xM3(), infinite loop
while looking for the bigger N-E RoutingPad. Forgot to decrement
the index...
* New: In ClockTree plugin, select the name of the buffer cell through
configuration (parameter: "clockTree.buffer"), and guess the I/O
name of this buffer automatically.
Put configuration parameters in plugin.conf and not mauka.conf.
Bug: strangely triggers a coredump in components collection
when used with <vsxlib>. Some debug printing still active until
that is solved.
* New: In Chip plugin, make the size and numbers of the block rails
configuration parameters (in plugin.conf).
Jean-Paul Chaput
Gabriel Gouvine