Basic BLIF parser for Yosys interface
This commit is contained in:
Gabriel Gouvine
parent
1aa416e82a
commit
18958d8f31
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@ -22,6 +22,7 @@
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${CRLCORE_SOURCE_DIR}/src/ccore/iccad04
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${CRLCORE_SOURCE_DIR}/src/ccore/cspice
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${CRLCORE_SOURCE_DIR}/src/ccore/lefdef
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${CRLCORE_SOURCE_DIR}/src/ccore/blif
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${CRLCORE_SOURCE_DIR}/src/ccore/alliance/ap
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${CRLCORE_SOURCE_DIR}/src/ccore/alliance/vst
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${CRLCORE_SOURCE_DIR}/src/ccore/agds
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@ -61,6 +62,7 @@
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crlcore/DefImport.h
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crlcore/DefExport.h
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crlcore/LefExport.h
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crlcore/Blif.h
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crlcore/AcmSigda.h
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crlcore/Iccad04Lefdef.h
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crlcore/Ispd04Bookshelf.h
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@ -151,6 +153,7 @@
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set ( iccad04_cpps iccad04/Iccad04Lefdef.cpp )
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set ( ispd04_cpps ispd04/Ispd04Bookshelf.cpp )
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set ( ispd05_cpps ispd05/Ispd05Bookshelf.cpp )
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set ( blif_cpps blif/BlifDriver.cpp )
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if ( LEFDEF_FOUND )
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include_directories ( ${LEFDEF_INCLUDE_DIR} )
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endif ( LEFDEF_FOUND )
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@ -296,6 +299,7 @@
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${iccad04_cpps}
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${ispd04_cpps}
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${ispd05_cpps}
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${blif_cpps}
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${spice_cpps}
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${lefdef_cpps}
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${openaccess_cpps}
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@ -905,7 +905,7 @@ association_element
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actual_port_name
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{ if (not Vst::states->_firstPass) {
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if ( Vst::states->_masterNets.size() != Vst::states->_instanceNets.size() ) {
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ostringstream message;
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ostringstream message;
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message << "CParsVst() VHDL Parser - File:<" << Vst::states->_vhdFileName.c_str()
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<< "> Line:" << Vst::states->_vhdLineNumber << "\n"
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<< " Port map assignment discrepency "
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@ -0,0 +1,269 @@
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// This file is part of the Coriolis Software.
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// Copyright (c) UPMC 2008-2014, All Rights Reserved
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//
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// +-----------------------------------------------------------------+
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// | C O R I O L I S |
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// | Alliance / Hurricane Interface |
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// | Yacc Grammar for Alliance Structural VHDL |
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// | |
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// | Author : Jean-Paul CHAPUT |
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// | E-mail : Jean-Paul.Chaput@asim.lip6.fr |
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// | =============================================================== |
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// | Yacc : "./VstParserGrammar.yy" |
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// | |
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// | This file is based on the Alliance VHDL parser written by |
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// | L.A. Tabusse, Vuong H.N., P. Bazargan-Sabet & D. Hommais |
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// +-----------------------------------------------------------------+
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#include <stdio.h>
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#include <string.h>
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#include <string>
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#include <sstream>
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#include <unordered_map>
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#include <unordered_set>
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#include <vector>
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using namespace std;
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#include "hurricane/Warning.h"
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#include "hurricane/Net.h"
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#include "hurricane/Cell.h"
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#include "hurricane/Plug.h"
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#include "hurricane/Instance.h"
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#include "hurricane/UpdateSession.h"
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using namespace Hurricane;
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#include "crlcore/Utilities.h"
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#include "crlcore/Catalog.h"
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#include "crlcore/AllianceFramework.h"
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#include "crlcore/NetExtension.h"
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#include "crlcore/Blif.h"
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using namespace CRL;
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namespace {
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using namespace std;
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// ---------------------------------------------------------------
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// Function : "SetNetType()".
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void SetNetType ( Net* net, AllianceFramework * framework )
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{
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if ( framework->isPOWER(net->getName()) ) {
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net->setType ( Net::Type::POWER );
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net->setGlobal ( true );
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} else if ( framework->isGROUND(net->getName()) ) {
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net->setType ( Net::Type::GROUND );
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net->setGlobal ( true );
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} else if ( framework->isCLOCK(net->getName()) ) {
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net->setType ( Net::Type::CLOCK );
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} else
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net->setType ( Net::Type::LOGICAL );
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}
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enum ParserState{
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EXT = 0x00,
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MODEL = 0x01,
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SUBCKT = 0x02,
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NAMES = 0x04,
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INPUTS = 0x08,
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OUTPUTS = 0x16
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};
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struct subckt{
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string cell;
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vector<pair<string, string> > pins;
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};
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struct model{
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string name;
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unordered_map<string, Net::Direction> pins;
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vector<subckt> subcircuits;
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bool operator<(model const & o) const{ return name < o.name; }
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};
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} // End of anonymous namespace.
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namespace CRL {
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//
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// Can only parse simple, netlist BLIF files generated by Yosys
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// Ignores all ".names" and uses only the .subckt, .model, .input and .output
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//
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Cell * Blif::load ( string cellPath ) //, Cell *cell )
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{
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using namespace std;
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auto framework = AllianceFramework::get ();
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std::ifstream ccell ( cellPath+".blif" );
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cmess2 << " " << tab << "+ " << cellPath << " [BLIF]" << endl;
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std::vector<model> models;
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ParserState state = EXT;
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bool hasName;
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string line;
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while(getline(ccell, line)){
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istringstream linestream(line);
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string before_comment;
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getline(linestream, before_comment, '#');
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istringstream tokens(before_comment);
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string token;
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while(tokens>>token){
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assert(not token.empty());
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if(token[0] == '.'){
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if(token == ".model"){
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if(state != EXT)
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throw Error("Nested model are not supported\n");
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state = MODEL;
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hasName = false;
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models.push_back(model());
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}
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else if(token == ".subckt"){
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if(state == EXT)
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throw Error("Subcircuit without an enclosing model are not supported\n");
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if(state == MODEL and not hasName)
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throw Error("Model has no name\n");
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state = SUBCKT;
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hasName = false;
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models.back().subcircuits.push_back(subckt());
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}
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else if(token == ".names"){
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cerr << Warning("BLIF names are ignored");
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if(state == EXT)
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throw Error("Names without an enclosing model are not supported\n");
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if(state == MODEL and not hasName)
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throw Error("Model has no name\n");
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state = NAMES;
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hasName = false;
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}
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else if(token == ".inputs"){
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if(state == EXT)
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throw Error("Inputs have been found without an enclosing model\n");
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state = INPUTS;
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}
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else if(token == ".outputs"){
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if(state == EXT)
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throw Error("Outputs have been found without an enclosing model\n");
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state = OUTPUTS;
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}
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else if(token == ".end"){
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if(state == EXT)
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throw Error("A .end has been found out of a model\n");
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state = EXT;
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}
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else{
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throw Error("Unexpected control token\n");
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}
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}
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else{ // Either a pin or an input/output definition
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if(state == INPUTS or state == OUTPUTS){
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auto it = models.back().pins.find(token);
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Net::Direction D = (state == INPUTS)? Net::Direction::DirIn : Net::Direction::DirOut;
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if(it != models.back().pins.end()){
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it->second = static_cast<Net::Direction::Code>(D | it->second);
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}
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else{
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models.back().pins.insert(pair<string, Net::Direction>(token, D));
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}
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}
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else if(state == SUBCKT){
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if(hasName){
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// Encountered a pin: need to be processed
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istringstream token_stream(token);
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string before_space, after_space;
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getline(token_stream, before_space, '=');
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getline(token_stream, after_space, '=');
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if(token_stream){
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Error("Encountered more than one '=' in token");
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}
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models.back().subcircuits.back().pins.push_back(pair<string, string>(before_space, after_space));
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}
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else{
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models.back().subcircuits.back().cell = token;
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hasName = true;
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}
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}
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else if(state == NAMES){
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// TODO; now just ignored
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}
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else if(state == MODEL){
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if(hasName)
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throw Error("Unexpected token after model name\n");
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else{
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models.back().name = token;
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hasName = true;
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}
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}
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else{
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throw Error("Unexpected token\n");
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}
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}
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}
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line.clear();
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}
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if(state != EXT){
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cerr << Warning("End of model has not been found");
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}
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for(auto & M : models){
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cout << "Model: " << M.name << endl;
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for(auto & S : M.subcircuits){
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cout << "\tInstance of " << S.cell;
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for(auto & P : S.pins){
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cout << " " << P.first << ":" << P.second;
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}
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cout << endl;
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}
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}
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if(models.size() > 1){
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cerr << Warning("Several models in the file; only the first was open");
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}
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Cell* design = framework->createCell(models[0].name);
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int i=0;
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for(auto & S : models[0].subcircuits){
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ostringstream subckt_name;
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subckt_name << "subckt_" << i;
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Cell * cell = framework->getCell(S.cell, Catalog::State::Views, 0);
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Instance* instance = Instance::create( design, subckt_name.str(), cell);
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unordered_set<string> net_names;
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for(auto const & P : S.pins){
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net_names.insert(P.second);
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}
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for(auto const & P : models[0].pins){
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net_names.insert(P.first);
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}
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for(string const & N : net_names){
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Net* new_net = Net::create( design, N );
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auto it = models[0].pins.find(N);
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if(it != models[0].pins.end()){
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new_net->setExternal( true );
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new_net->setDirection( it->second );
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}
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}
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for(auto & P : S.pins){
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Net* internalNet = cell->getNet( P.first );
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Net* externalNet = design->getNet( P.second );
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instance->getPlug( internalNet )->setNet( externalNet );
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}
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++i;
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}
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return cell;
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}
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}
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@ -0,0 +1,63 @@
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// -*- C++ -*-
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//
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// This file is part of the Coriolis Project.
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// Copyright (C) Laboratoire LIP6 - Departement ASIM
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// Universite Pierre et Marie Curie
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//
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// Main contributors :
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// Christophe Alexandre <Christophe.Alexandre@lip6.fr>
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// Sophie Belloeil <Sophie.Belloeil@lip6.fr>
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// Hugo Clément <Hugo.Clement@lip6.fr>
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// Jean-Paul Chaput <Jean-Paul.Chaput@lip6.fr>
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// Damien Dupuis <Damien.Dupuis@lip6.fr>
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// Christian Masson <Christian.Masson@lip6.fr>
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// Marek Sroka <Marek.Sroka@lip6.fr>
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//
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// The Coriolis Project is free software; you can redistribute it
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// and/or modify it under the terms of the GNU General Public License
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// as published by the Free Software Foundation; either version 2 of
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// the License, or (at your option) any later version.
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//
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// The Coriolis Project is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty
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// of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with the Coriolis Project; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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// USA
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//
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// License-Tag
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// Authors-Tag
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// ===================================================================
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#ifndef CRL_BLIF_H
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#define CRL_BLIF_H
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# include <string>
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namespace Hurricane {
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class Cell;
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}
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namespace CRL {
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using Hurricane::Cell;
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class Blif {
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public:
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static Cell* load ( std::string netlist );
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};
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} // End of CRL namespace.
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# endif
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@ -28,6 +28,7 @@
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#include "crlcore/AcmSigda.h"
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#include "crlcore/Ispd04Bookshelf.h"
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#include "crlcore/Ispd05Bookshelf.h"
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#include "crlcore/Blif.h"
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#include "crlcore/Iccad04Lefdef.h"
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#include "crlcore/DefImport.h"
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#include "crlcore/DefExport.h"
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@ -51,6 +52,7 @@ namespace Unicorn {
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using CRL::AcmSigda;
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using CRL::Ispd04;
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using CRL::Ispd05;
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using CRL::Blif;
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using CRL::Iccad04Lefdef;
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using CRL::DefImport;
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using CRL::DefExport;
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@ -87,6 +89,7 @@ namespace Unicorn {
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_importCell.addImporter( "ACM/SIGDA (aka MCNC, .bench)", std::bind( &AcmSigda::load , placeholders::_1 ) );
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_importCell.addImporter( "ISPD'04 (Bookshelf)" , std::bind( &Ispd04::load , placeholders::_1 ) );
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_importCell.addImporter( "ISPD'05 (Bookshelf)" , std::bind( &Ispd05::load , placeholders::_1 ) );
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_importCell.addImporter( "BLIF (Yosys/ABC)" , std::bind( &Blif::load , placeholders::_1 ) );
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_importCell.addImporter( "ICCAD'04 (LEF/DEF)" , std::bind( &Iccad04Lefdef::load, placeholders::_1, 0 ) );
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_importCell.addImporter( "Alliance compliant DEF" , std::bind( &DefImport::load , placeholders::_1, DefImport::FitAbOnCells) );
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}
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