* Change: In CRL/helpers.Trace, flush stderr before issuing the trace
message to avoid mixing up stdout & stderr (sometimes misleading).
* Change: In CRL/helpers.overlay.CfgCache, no longer display all the
applied setting after a call to apply(). Too verbose.
* Change: In CRL::Environment, regex_t are now pointers instead of values,
this way the "in initialization" flag can be removed (maybe still too
complicated).
* Bug: In Anabatic::AutoHorizontal::_slacken(), when creating the target
dogleg, if the target was a fixed pin (M2) on the east side, the
vertical was put righ on the side, which is *not* an allowed track.
The exact east side is not covered by a vertical track (this comes
from a policy adpopted for the GCell, to avoid overlapping tracks
on the border). So we got an error message when katana tries to
bind it to a track. Now shift one perpandicular pitch to the *left*
for the EAST pins.
* Bug: In Coloquinte::rough_legalizer, when running in debug mode,
some assert where popping up. But, in normal mode the placer
just went fine. So we assume they where too broad in their
scope. Commented out.
* Change: In Anabatic::NetBuilderHV::_do_1G_xM1_1PinM2(), the M2 pin
(horizonal) was directly aligned with the outgoing global through
a H-Tee. This was too rigid. Now it can be misaligned.
* New: In Katana::Manipulator::moveUp(), if the length of the wire is
greater than 60 pitchs, increase the reserve from 0.5 track to
1.0 track. This is to left more free tracks when lots of very
long segments are moved up. Make the run 17 of the ARM test bench
pass.
* Change: In AnabaticEngine::_desaturate(), now use a STL priority
queue built upon a vector with duplicates of the GCell keys.
Much much more faster than the previous set with a custom
sorting key over the GCell. Insertion & removal where getting
a lot of time. Now it's down to less than a minutes, even for
big designs.
* Change; In Anabatic::GCells, add the ability to clone the GCell
key, to use it independently in GCells sorting containers.
This way the cloned value do not change when the GCell is
updated. Keep track of the latest (most up to date) cloned
key.
* New: In CRL/helpers.overlay.CfgCache, add support for context manager,
so we can progressively remove the use of Configuration. One class
to use in all contexts (immedaite setting or storing a set of
Cfg parameters).
* Bug: In Etesian::toColoquinte(), inadvertently stopped taking into
account fixed instances... Compute correctly the number of
instances to place (all instances minus fixed ones..).
* Bug: In cumulus/plugins/block/block.py, when a block is found to have
a layout, that is, is already placed & routed, it's instances must
be flagged as FIXED instead or PLACED so Etesian will really sees
them as unmovable and don't account them to be placed.
* New: In EtesianEngine::toColoquinte(), fixed blocks must not be
accounted as instances to be placed.
When, there is no instances to place, just issue an error message
and return.
* Bug: In Anabatic::NetBuilderHV::_do_2G_xM1_1PinM2(), in the case of a
bend of global wires, the topology was faulty. Too rigid topology,
the global wire was forcibly aligned on the external Pin.
* New: In Katana::Configuration, two new parameters hTrackReservedMin
and same for V. Forced decrease of all edges capacities, to use
when the global router is too optimistic...
* New: In EtesianEngine::setDefaultAb(), add computation of AB when
using fixed width (fixed height) was already available.
Add attribute management for the fixed width along with a
Python export.
* New: In Anabatic::AutoContactTerminal, new method "isOnPin()" to
know if the terminal contact is on a Pin. Introduced in base
class.
* Bug: In Anabatic::AutoHorizontal::_canSlacken() & AutoVertical,
forbid slackening from a Pin. As Pin are all on the side of the
cell (aligneds) and the perpandicular segment will be locked on
the Pin, it generates intractable overlaps for the router.
* Bug: In Anabatic::Configuration::selectRpComponent(), always select
the Pin as the best component. It is mandatory for a block that
we pick up the terminal at the periphery and not one deep inside
the block.
* Bug: In Hurricane::RoutingPad::setOnBestcomponent(), same rule as
in Anabatic, if there is any, the Pin must always be the best
RoutingPad component.
* New: In CRL/helpers/overlay.py, CfgCache class to hold a set of
configuration parameters and apply it on demand. It has a
different behavior than Configuration.
* Bug: In Hurricane/Commons.h, modify the getRecord<>() templates so
that for both vector<Element> and vector<Element*>, the individual
record created for each element are donne with pointers. That is,
for the vector<Element> case, we take a pointer.
As a general policy, except for the POD types, always use pointers
or references to data in the records/inspector. Never uses values
that can call the copy constructor.
Suppress INSPECTOR_PV_SUPPORT() macro, keep only
INSPECTOR_PR_SUPPORT().
Provide value support only for getString<>() template.
This value & copy constructor problem was causing a crash when
trying to inspect Hurricane::AnalogCellExtension.
* New: In Hurricane::Technology, change the API of the PhysicalRule,
now we can only create/get PhysicalRule, but setting the value of
the rule itself must be done on the rule.
Enhance PhysicalRule to provide for stepped rules, non isotropic
and ratio rules.
Merge TwoLayersPhysicalrule in PhysicalRule, much simpler to
suppress the management of derived classes. That means that we
loose a little memory as some fields are mutually exclusive.
Not a problem considering that there will not be so many of thoses
objects.
* New: In CRL/helpers.analogtechno.py, enhanced DTR support for rules
like:
('minSpacing' , 'metal1', ((0.4,20.0), (0.8,1000.0)), Length, 'REF.1')
('minEnclosure', 'metal1', 'cut1', (0.2,0.3) , Length, 'REF.2')
('minDensity' , 'metal1', 0.30 , Unit , 'REF.3')
The DTR parser has been updated, but not the oroshi.dtr Rule
cache for analog components. Given a rule name, the value used
will be the horizontal one of the first step.
* Change: In hurricane/doc/hurricane, re-generate the documentation
with updated support for Technology & PhysicalRule.
* Bug: In EtesianEngine::place(), reset the placement *only* if we are
*not* placing a sub-block *and* the top cell abutment box is empty.
* Bug: In EtesianEngine::place(), set the instance placement status of
all intermediate instances to PLACED, so the AP driver will save
them (we were having partially saved layout when using hierarchical
designs).
* Bug: In EtesianEngine::resetPlacement(), reset the PLACED flag and
the abutment box on the top cell or sub-block to be placed.
* Change: In CRL/helpers/__init__.py, to ensure a complete restart of
the database the __init__.py must be called again, but it's not the
case with reload() (see Python doc). So helpers.resetCoriolis()
must explicitly removes the Coriolis related Python modules from
sys.modules (calling "del sys.modules[moduleName]").
That list of Coriolis Python modules is built by calling
helpers.tagConfModules(), it will tag all modules added to
sys.modules since startup. It will remove (much) more than
Coriolis modules, but that should be ok.
* Change: In CRL/etc/{node*,symbolic}/TECH/__init__.py, add a call to
helpers.tagConfModules() for the techno modules to be erased on
reset.
* New: In Anabatic::NetBuilder, some GCells configurations of Libre-SOC
"test_issuer" (soclayout/experiments9) did have more METAL1 terminals
than was though possible. Just added more entries in the connexity
table for bigger numbers of METAL1. No new configuration was added,
used the already existing ones.
* Bug: In cumulus/plugins/rsave.py, use "Cell.isTerminalNetlist()"
instead of "Cell.isTerminal()" to find the hierarchical stop
points.
If the root cell to be saved is itself a *terminal netlist*
one, save it anyway. The top level *must* be saved regardless to
it's status.
* Bug: In CRL/Vhdl::VectorPortMap::toVhdlPortMap(), two problems:
1. Bad condition for the use of VstUseConcat. Must be used *only*
when there is more than *one* mapped name.
2. Missing case, when there is exactly *one* mapped name, that
means that we have one full width vector to vector assignement.
There may be another weakness here, for the portmap we assumes
that both vector are mapped in the *same* direction (which is
"downto" by our convention).
3. In the "bit by bit mapping case" (every bits of the vector are
differents bits), use the "signal + bit index" name instead of
juste the signal name (i.e. full width).
Solves the Libre-SOC/soclayout/experiment6/fpmul64 problem, now
we can avoid the YOSYS_FLATTEN.
* Change: In Vhdl:::Signal::toVhdlPort(), in Alliance VST signal with
undefined directions are typed "linkage". This may not be compatible
with vasy, so allow to replace them by "in".
* New: In CRL::Catalog::State, add a new flag VstNoLinkage to tell if
the VST driver should not use the "linkage" type.
* Change: In Vhdl::Entity, add a VstNoLinkage flag to disable the use
of the "linkage" type.
Jean-Paul Chaput
Marie-Minerve Louërat