Commit Graph

2324 Commits

Author SHA1 Message Date
Jean-Paul Chaput 5bbeb0b062 Support for separated NDA tree. Big cleanup of the Python init system.
* Change: In Hurricane::Script, when running a script, no longer do it
    inside a Python sun-interpreter, use the current one. This way we
    no longer have our modules initialized twice or more, which was
    starting to be unmanageable (with the NDA support).
      The settings were re-read multiple time to the same value, so it
    was working, but still...
      I hope I didn't left some dangling Python objects now.
* Bug: In Hurricane::LayoutGenerator::drawLayout(), get the device abutment
    box though a Pyhon object *before* finalizing which removes that objet.
* New: In cumulus/plugins/__init__.py, add a "loadPlugins()" and static
    initialisation to preload plugins modules.
      We use that pre-loading step to append to the module __path__ attribute
    the alternate directory where a NDA covered may be found. This assume that
    the directory tree under the NDA root is identical to the one under the
    public root.
* New: In cumulus/plugins/chip/__init__.py, small utility function
    importContants() to import the constants inside another module namespace,
    to have more consise notations.
* Change: In cumulus/plugins/, in the various plugins sub-modules import
    use the full path from plugins, that is, for example:
      from plugins.core2chip.CoreToChip import IoPad
* Change: In Unicorn/python/unicornInit.py, no longer directly load the
    plugins modules, this is now done by cumulus/plugins/__init__.py.
      Instead, iterate through sys.modules for the ones starting by "plugins/"
    and try to execute a Unicorn hook, if present.
* Change: In Karakaze/python/AnalogDesign.py, update for the new Instance.create()
    prototype (added placement parameter).
2019-10-11 17:36:54 +02:00
Gabriel Gouvine ae98b117ba Handle fixed pins on a net 2019-10-06 12:58:49 +02:00
Gabriel Gouvine a90b5ed890 Partial support of newer Bookshelf formats 2019-10-06 12:58:42 +02:00
Gabriel Gouvine f1644fc229 Workaround to get the ISPD benchmarks working 2019-10-06 12:58:33 +02:00
Jean-Paul Chaput 5914e16f26 Added management for "phlib" I/O pad external connectors (for cougar/lvx).
* New: In CRL::ApDriver::DumpSegments(), drive as top-level segments the
    RoutingPads using a Pin, and not only using a segment. They are not
    exported as top level Pin but only as Segment as they do belong to
    a deeper level.
* New: In Cumulus/plugins/PadsCorona.Side._placePads(), now manage both
    "pxlib" and "phlib*". Pad library management is still hardcoded, this
    should be made a configuration option someday.
2019-10-05 16:04:12 +02:00
Jean-Paul Chaput 02b30b6681 More terse failure message from the global router.
* Bug: In CRL::cstDriver(), re-activate the management of the VstUseConcat
    flag. Why was he removed in the first place?
* Change: In KatanaEngine::runGlobalRouter(), no longer give the details of
    each overflowed edge and the complete list of impacted nets.
    Only a count.
2019-09-29 18:35:16 +02:00
Jean-Paul Chaput 6faf83309e Force pitching on dragged AutoContacts.
* Change: In Anabatic::AutoContactTerminal::updateGeometry(), when a
    draggable AutoContact is moved, pitch it on the routing grid instead
    of putting it in lowest/highest position.
2019-09-26 01:16:01 +02:00
Jean-Paul Chaput 2bd18313d1 More tuning for ARMv2a (95% success, 38/40). Bugs in core2chip.
* Change: In Anabatic::GCell::updateDensity(), all non-passthrough wires
    now have a cost of 0.5 instead of 0.33 for locals.
* Change: In Manipulator::canMoveUp(), increase the "reserve" amount to
    1.0 for "far from terminal" wires (rpDistance > 2).
* Change: In NegociateWindow::NegociateOverlapCost(), always sets "AtRipupLimit"
    when the overlapping segment is nearing it's maximum ripup limit.
    (different detection for non-preferred and regular)
* Change: In SegmentFsm::_slackenStrap(), call avoidBlockage() if it is
    overlapping a blockage *or* a segment at it's ripup limit. I hope I
    didn't create an infinite loop here.
* Bug: In cumulus/plugins/PadsCorona.py, CoreWire._computeCoreLayers(),
    the big contact between symbolic and real was badly computed for
    east/west (was using width instead of height, bummer!).
      In Corona._createCoreWire(), completly screwed computation of the
    side gap, was using a badly initialized value of the "bb" variable.
* Bug: In cumulus/plugins/Chip.py, the computation of the minimal size
    for the corona was wrong, do *not* add the size of the pads and
    multiply by two as it is done by "inflate". This was forcing the user
    to create way to large chips for a given core size.
2019-09-25 18:35:03 +02:00
Jean-Paul Chaput d7931391c0 Adjusted routing pitch for METAL4 to METAL7 for FreePDK45 symbolic. 2019-09-19 23:52:03 +02:00
Jean-Paul Chaput 24dedce09c Added core2chip support for Phenitec80.
This commit degrades the run success rate of ARMv2a to 87% (40 iters).
* New: In CRLcore/etc/.../kite.conf, add configuration parameters:
      katana.termSatReservedlocal
      katana.termSatthreshold
    for the new edge capacity computation system.
* New: In CRLcore/etc/symbolic/phenitec06/, add support for N. Shimizu
    small I/O pads (supplied in phlib80). Tune various parameters of
    Anabatic/Katana to increase routing success.
* Change: In CRLcore/alliance/ap/ApParser, make Pin external components,
    so RoutingPad will be build upon in global routing.
      Do not complain when a I/O pad has a physical instance that did
    not exists in the netlist. Just create it (appeared in phlib80).
      When no netlist instance exists in a pad, the pad Cell is still
    considered as terminal.
* New: In Etesian::BloatCells, new profile named "3metals" better suited
    for two routing metals technologies (i.e. Phenitec).
* New: In Anabatic::RawGCellsUnder, new CTOR which take only source &
    target points instead of a segment. Needed to manage wide segment for
    which the axis to consider is not that of the segment (one axis for
    each track it intersect).
* New: In Anabatic::GCell, add a RoutingPad count attribute, for Edge
    reservation computation.
* New: In AnabaticEngine::computeEdgeCapacities(), instead of decreasing
    all edges of a fixed amount (hTrackReservedLocal), guess the GCell
    cluttering from the number of RoutingPads that it contains.
      For non-saturated GCells, the four edges are decreased by the number
    of RoutingPads. We use the maximum from the two neigboring GCells.
    The hTrackReservedLocal parameter is now used only as a *maximum*
    that the edge reservation can reach.
      If a GCell is saturated (more than 8 RoutingPads, the saturation is
    propagated horizontally to 2 neigboring GCells).
* Change: In AutoContactTerminal::getNativeConstraintBox(), use a more
    flexible gauge name matching for terminal vertical extensions correction.
    Namely, match all "msxlib*" kind of gauges.
* Change: In AutoSegment::setAxis(), add the ability to force the axis
    position, even if it is a non-canonical segment. Maybe needed in the
    initialisation steo, before the first canonisation is performed.
* New: In NetBuilder, added new methods _do_1G_1PinM1() and _do_2G_1PinM1(),
    to manage coronas for Phenitec designs.
      To avoid various side effects from segments being too close from
    the north / east side of the routing area, make those segments fixeds.
* Change: In KatanaEngine::annotateGlobalGraph(), the management of wide
    wires was wrong. The axis to use to find the underlying GCells is the
    one of the track, not of the segment. This was creating bad edge
    capacity computation under the power ring of a block and subsequently
    routing failures.
* New: In Kanata::Manipulator, added method reprocessParallels(), not used
    though, but keep it anyway, might be of use later...
* New: In Kanata::Manipulator, added method avoidBlockage() for terminal
    METAL2 in non-preferred direction, restrict the terminal and turn
    constraint box at the current position of the perpandicular, so it
    doesn't create a deadlock in METAL2.
* Change: In SegmentFsm::conflictSolveByPlaceds(), if we cannot break
    using the whole overlap, try the first atomic overlap.
* New: In SegmentFsm::_slackenStrap(), manage conflict between a non-prefered
    segment and a blockage, this when to call avoidBlockage()...
* New: In Katana::Configuration, management of the new edge computation
    parameters:
      katana.termSatReservedlocal
      katana.termSatthreshold
* New: In Cumulus/plugins/Core2Chip, support for Phenitec I/O pads.
2019-09-17 17:05:54 +02:00
Jean-Paul Chaput c6ea1bccdd Improvements in routing quality for ARMv2a, reached 100% success.
Now reliably work for 20 successive runs (doRun.sh) with pseudo-random
variations.
* Change: In AnabaticEngine::computeNetConstraints(), fully recompute
    the "distance to RoutingPads" for all AutoSegments.
      Previously we tried to do it incrementally, but as it's computed
    as a minimum, it stayed stuck at the lowest value, event after a
    net's change of topology that could made it increase (a new dogleg
    did appear between the segment and the RoutingPad).
2019-08-23 23:48:09 +02:00
Jean-Paul Chaput 02eb5c56ad Improvements in routing quality for ARMv2a
* Change: In Katana::SegmentFsm::_slackenStrap(), make unbreakable segments
    pass through the LocalVsGlobal state so when other try to ripup them
    they are prioritary. Otherwise some could go through Unimplemented
    directly, without allowing other to attempt to make a detour.
* Change: In Katana::NegociateWindow::NegociateOverlapCost(), when a
    global, which is about to be slackened wants to use a track where there
    is a segment directly connected to a terminal with a significant
    ripup count, mark it as "AtRipupLimit" so it tries to avoid it.
      The idea is that globals with high ripup count must avoid terminal
    segments because it is likely they will be riped up again so they
    better find another track. This was leading to unsolvable configuration
    when two segments always want the same track. In this cas, the global
    would loose.
* Bug: In Katana::TrackSegment::canSlacken(), never slacken a segments in
    non-preferred direction.
* Change: In Anabatic::AutoHorizontal::_slacken(), allow slackening of
    segments which perpandiculars are in non-preferred direction, and
    not only directly attached to terminals.
* Change: In Anabatic::AutoSegment::canMoveUp(), re-allow segments which
    perpandiculars are in non-preferred direction to be moved up.
* Bug: In Katana::Manipulator::moveUp(), when moving up, do not forget
    to ripup and reschedule said segment.
2019-08-23 15:43:13 +02:00
Jean-Paul Chaput 1124e92ac2 Correcting non-deterministic behavior in Anabatic/Katana (again).
This non-deterministic behavior was showing only in the ARMv2a benchmark
around event 180k...
* Bug: In Anabatic::Session::_netInvalidateds & _netRevalidateds, the
    set<> was still sorted on pointers. As contacts & segments can be
    created to maintain connexity after a layer change, we got a
    discrepency in objects Ids that may generate a change in ordering
    later.
* Bug: In Katana::Session::_doRemovalEvents(), the set of Tracks that
    got elements deleted was still using pointers. Now we use a TrackSet
    sorted on (direction,depth,axis). This should not have created
    a change in the results, as destructions do not change Ids, but it
    genereate extra differences in traces.
2019-08-20 16:30:03 +02:00
Jean-Paul Chaput 014dbe1bcc Bug in segment layer reduction causing METAL2 to go in METAL1 (RISC-V).
* Bug: In Anabatic::AutoSegment::reduceDoglegLayer(), we did not check
    that not only source and target depth span was zero, but also both
    on the same one. This was seen in the RISC-V where a METAL2 small
    segment was demoted into METAL1 causing a gap in the routing (and
    a short in the underlying standart cell).
2019-08-18 13:20:50 +02:00
Jean-Paul Chaput 91f973c00f Improve the management of the I/O pad near the chip corner.
* Bug: In cumulus/plugins/PadsCorona.py, when a pad is at the beginning
    or at the end of the side, the pad corona terminal may be outside
    the corona range (not directly facing it). In that case, create a
    bend to reach it.
      Worse, in some case more than one (but likely no more), could be
    in that case, so not only do we create a bend but also make a
    shift in the bended segment so two consecutive ones are not on the
    same axis, causing shorts.
      If both end pads of a corner are in that case, we cannot prevent
    a short, so at least, issue a warning.
* Bug: In CRL::Vhdl, the Entity::VstUseConcat was not passed correctly
    along, so we did get a strange mix of conat and direct assignment.
* New: In Unicorn/cgt.py : added --vst-use-concat options to control
    the VST driver behavior.
2019-08-16 00:40:49 +02:00
Jean-Paul Chaput f92b48174b Correct management of "fused_net" in Alliance parser/drivers.
* Bug: In CRL::ApDriver & CRL::ApParser, when saving a fused net, do not
    use it's name but put a star (*) character to set it anonymous.
      Having all component named was creating problems in cougar and
    subsquently in yagle (bad name for master latch).
      Conversely, in the parser, if the name of the net is "fused_net",
    make it a real fused_net and not an ordinary one.
2019-08-15 01:59:38 +02:00
Jean-Paul Chaput 5877691cde The VST driver can now be setup to use or not concat ('&') in PORT MAP.
* New: In CRL::AllianceFramework::saveCell(), through the view flag we
    can pass an option 'CRL::Catalog::State::VstUseConcat' to tell the
    driver tu use or not the concat '&' in PORT MAP statements.
      It is not completely clean that the flag for controlling the VST
    driver behavior is put in the Catalog states, but it's easier for
    now...
      And, of course, exported at Python level.
2019-08-13 14:46:23 +02:00
Jean-Paul Chaput d670de4125 Added support for 3 metal layers symbolic Phenitec 0.6um.
* New: In CRL/etc/symbolic/phenitec06, configuration for symbolic
    layout targeted for Phenitec 0.6um (do not contains any NDA
    covered informations). Could be used for any 3 metal layers
    techno.
* Bug: In Cumulus/plugins/chip/Configuaration.py, _setStackposition()
    disable stack error when there is no slave component on the stack
    (happens when the stack consists only of one contact).
2019-08-12 15:41:17 +02:00
Jean-Paul Chaput 4b9a6ec4a9 Ensure that there is at least one free GCell on each side of the corona.
* Change: In Cumulus/plugins/chip/PadsCorona, if the external pins of
    the corona are in GCells that are also under the core block ring
    power lines, they are flagged as "go straight" and this produce
    impossible configurations for the router to solve. Now we ensure
    that there is one free GCell all around the corona border.
* Bug: In Cumulus/plugins/chip/Configuration.py & PadsCorona.py,
    at the begin/end of a side of pad, connectors can be outside the
    corona range (i.e. not directly face to face). Now make a dogleg
    if needed. This is a work in progress as if there are two of them,
    they will short on the perpandicular part. We must compute a
    shift.
2019-08-12 01:11:58 +02:00
Jean-Paul Chaput 1b2c90424a Do not slacken segments which source/target in a "go straight" GCell.
* Change: In Anabatic::AutoHorizontal::_canSlacken(), if the source or
    target contact is in a GCell flagged "go straight", do not slacken,
    which would create a dogleg. This case is usually meet under big
    power rails that render a dogleg impossible to place as all tracks
    are used.
       Same modification for AutoVertical.
2019-08-12 01:01:29 +02:00
Jean-Paul Chaput 70a3960ba5 ioNet used as "enable" should not get the name of the pad.
* Bug: In Cumulus/plugins/core2chip/CoreToChip.py, when creating the ioNet
    objects, when a signal is an enable we must not set the external chip
    net (the name for the PAD terminal) as it may be set later if it is
    also used as an individual pad.
2019-08-09 18:45:19 +02:00
Jean-Paul Chaput 15cd9187de Allow enable signal of bidir pads to be exported in Core2Chip.
* Change: In Cumulus/plugins/core2chip/CoreToChip.py, in IoNet select
    the external I/O net (pad connected) signal to be generated in the
    context of the I/O pad instanciation. This should allow an enable
    signal in one pad to be also used in a direct output pad.
2019-08-09 12:56:54 +02:00
Jean-Paul Chaput e80fcd8648 Remove VHDL driver extension/property after use.
* In CRL::vstDriver(), remove the Vhdl::EntityExtension right after driving
    the file. This avoid keeping in memory a mostly usnused structure and
    solve the "second write after modification" problem.
2019-08-08 14:12:22 +02:00
Jean-Paul Chaput 86c4e9cb17 Added support for Tristate and bidir pads in CoreToChip.
* New: In Cumulus/plugins/CoreToChip, added support for Tristate ouput
    pads and bidirectional pads.
      Added capability to name the I/O pad instance and their external
    terminals so we can override the default naming scheme.
      Mandatory anyway for bidirectional and tristate I/O pad as we
    cannot guess the core net grouping (in/out/enable).
      Support is available for symbolic CMOS and AMS c35b4 (but not
    published due to NDA).
* Change: In Cumulus/plugins/chip/Configuration.py, the configuration
    file is now named simply "ioring.py" instead of being prefixed by
    the design name. As a consequence we can have only one chip per
    directory. But now all the tools, for any design in that directory
    can peek datas into it.
2019-08-08 00:57:19 +02:00
Jean-Paul Chaput acc3a38f60 Support for placing *one* block of a Cell in Etesian.
* Change: In Hurricane::Cell_LeafInstanceOccurrences, add the ability to
    walkthrough the leaf of one specific top-level instance.
* Change: In Hurricane::Cell_NonLeafInstanceOccurrences, add the ability to
    walkthrough the leaf of one specific top-level instance.
* Change: In Hurricane::Cell:
    getLeafInstanceOccurrences() and getNonLeafInstanceOccurrences(), now
    have a parameter Instance* to select the leafs we want to walk through.
    If set NULL (default value) browse through all the instances,
    as before.
* Change: In Hurricane::DeepNet, add forgotten Inspector support.
* New: In EtesianEngine, add a "block" (and Instance) attribute to allow
    the placement of one specific bloc. If we want to place the core of
    a chip and take into account the external terminals (if they are not
    already fixed as Pins at the edge of *said* block). We must place
    the core *in the context* of it's instanciation in the corona.
      Note for G. Gouvine : Pin & external RP should be taken into account
    starting at line 629 of EtesianEngine.cpp...
* New: In cumulus/plugins/chip/Chip.py, make use of the new block
    placement feature of ETesian.
* Bug: In KatanaEngine::create(), perform a pre-check to prevent trying to
    route whole chip, which is forbidden an leads to annoying core-dumps.
    Routing must take place "at most" at Corona level.
* Bug: In KatanaEngine::PowerRails, create a plane for METAL1 blockage.
    Not completely sure this was a bug...
2019-08-04 17:33:03 +02:00
Jean-Paul Chaput 1b444d8f49 In cumulus/Core2Chip.py forgot a parameter to an error message call. 2019-07-31 19:16:40 +02:00
Jean-Paul Chaput 1359fe4ba6 Change Net name merge policy in the Blif parser.
* Change: In CRL/BlifParser::Model::mergeAlias(), do not always merge the
    net2 with net1 (RHS with LHS of the ".name" instruction). This may
    result in a name change in the design interface (external net).
      Instead, merge any internal net with the external, so keep the
    external net name. If both are external, keep the one with the lower
    id (which should have been created first).
2019-07-31 18:29:22 +02:00
Jean-Paul Chaput 85e969bca9 Disable the use of concat '&' in VST port map. 2019-07-31 17:38:35 +02:00
Jean-Paul Chaput d69327d9a9 Various typos correction (courtesy of G. Gouvine). 2019-07-30 13:13:57 +02:00
Jean-Paul Chaput f528cdea4c Upgrade of Katana detailed router to support Arlet 6502.
* Change: In Hurricane::SharedName, replace the incremental Id by a hash key.
    This is to ensure better deterministic properties. Between use cases,
    additional strings may have to be allocated, shitfing the ids. Even if
    hash can be duplicated, we should be able to ensure that the absolute
    order in map table should be preserved. Supplemental strings are inserted
    in a way that keep the previous order.
* Change: In CRL/etc/symbolic/cmos/kite.conf, add "katabatic.routingGauge"
    default parameter value ("sxlib").
* Change: In CRL/etc/common/technology.conf, define minimal spacing for
    symbolic layers too (added for METAL4 only for now).
* Change: In CRL::Histogram, extend support to dynamically sized histograms.
    Add a text pretty print with table and pseudo-curve.
* Change: In Cumulus/plugins/ClockTreePlugin, create blockage under the
    block corona corners so the global router do not draw wire under them.
    This was creating deadlock for the detailed router.
      When the abutment has to be computed, directly use Etesian to do it
    instead of duplicating the computation in the Python plugin.
* New: In Etesian, as Coloquinte seems reluctant to evenly spread the
    standard cells, we trick it by making them bigger during the placement
    stage. Furthermore, we do not not uniformely increase the size of the
    cells but create a "bloating profile" based on cell size, cell name
    or it's density of terminals. Currently only two profiles are defined,
    "disabled" which does nothing and "nsxlib" targeted on 4 metal layer
    technologies (aka AMS 350nm, c35b4).
* Bug: In Knik::MatrixVertex, load the default routing gauge using the
    configuration parameter "katabatic.routingGauge" as the default one
    may not be the first registered one.
* New: In AnabaticEngine::setupNetDatas(), build a dynamic historgram of
    the nets terminal numbers.
* Bug: In Anabatic::AutoContact::Invalidate(), always invalidate the
    contact cache when topology is invalidated. In case of multiple
    invalidations, if the first did not invalidate the cache, later one
    that may need it where not allowed to do so. The end result was correct
    nonetheless, but it did generate annoying error messages.
* Bug: In Anabatic::AutoContactTurn::updateTopology(), bad computation
    of the contact's depth when delta == 2.
* Bug: In Anabatic::Gcell::getCapacity(), was always returning the west
    edge capacity, even for the westermost GCell, should be the east
    edge in that case.
* New: In Anabatic::AutoSegment, introduce a new measure "distance to
    terminal". This is the minimal number of segments separating the
    current one from the nearest RoutingPad. This replace the previous
    "strong terminal" and "weak terminal" flags.
      This distance is used by Katana to sort the events, we route the
    segments *from* the RoutingPads *outward*. The idea being that if we
    cannot event connect to the RoutingPad, there is no points continuing
    as thoses segments are the more constraineds. This gives an order close
    to the simple ascending metals but with better results.
* New: In Anabatic::AutoSegment, introduce a new flag "Unbreakable", disable
    dogleg making on those segments. mainly intended for local segments
    directly connecteds to RoutingPads (distance == 0).
* New: In Anabatic::AutoSegment, more aggressive reducing of segments.
    Now the only case where a segment cannot be reduced is when it is
    one horizontal branch in a HTee or a vertical on a VTee. Check if,
    when not accounted the source & target VIAs are still connex, if so,
    allow reducing.
* New: In Anabatic::AutoContact, new state flags CntVDogleg & CntHDogleg
    mainly to prevent making doglegs twice on a turn contact. This is to
    limit over-fragmentation. If one dogleg doesn't solve the problem,
    making a second one will make things worse only...
* Bug: In Anabatic::Configuration::selectRpcomponent(), we were choosing
    the component with the *smallest* span instead of the *bigger* one.
* New: In Anabatic::GCell, introduce a new flag "GoStraight" to tell that
    no turn go be made inside those GCells. Mainly used underneath a block
    corona.
* New: In AnabaticEngine::layerAssign(), new GCellRps & RpsInRow to manage
    GCells with too many terminals. Slacken at least one RoutingPad access
    when there is more than 8 RoutingPad in the GCell (slacken or change
    a vertical METAL2 (non-preferred) into a METAL3).
* Change: In Anabatic::NetBuilderHV, allow the use of terminal connection
    in non-preferred direction. That is, vertical METAL2 directly connected
    to the RoutingPad (then a horizontal METAL2). This alllows for short
    dogleg without clutering the METAL3 layer (critical for AMS c35b4).
      Done in NetBuilderHV::doRp_Access(), with a new UseNonPref flag.
      Perform some other tweaking on METAL1 access topologies, to also
    minimize METAL3 use.
* New: In AnabaticEngine::computeNetConstraints(), also compute the
    distance to RoutingPad for segments. Set the Unbreakable flag, based
    on the distance and segment length (local, short global or long global).
      New local function "propagateDistanceFromRp()".
* Change: In AnabaticEngine.h, the sorting class for NetData, SparsityOrder,
    is modificated so net with a degree superior to 10 are sorted first,
    whatever their sparsity. This is to work in tandem with GlobalRouting.
* New: In Katana::TrackSegmentNonPref, introduce a class to manage segment
    in non-preferred routing direction. Mostly intended for small METAL2
    vertical directly connected to RoutingPad. Modifications to manage
    this new variant all through Katana.
* Change: In Katana::GlobalRoute, DigitalDistance honor the GoStraight flag
    of the GCell. Do not make bend inside thoses GCells.
* Change: In KatanaEngine::runGlobalRouter(), high degree nets (>= 10) are
    routed first and whitout the global routing estimation. There should be
    few of them so they wont create saturations and we want them as straight
    as possible. Detour are for long be-points.
      Set the saerch halo to one GCell in the initial routing stage (before
    ripup).
* Bug: In KatanaEngine & NegociateWindow, call _computeCagedconstraints()
    inside NegociateWindow::run(), as segments are inserted into tracks
    only at that point so we cannot make the computation earlier.
* Change: In Katana::Manipulator::repackPerpandiculars(), add a flag to
    select whether to replace the perpandiculars *after* or *before* the
    current segment.
* Change: In Katana::NegociateWindow::NegociateOverlapCost(), when the
    segment is fully enclosed inside a global, the longest overlap cost
    is set to the shortest global hoverhang (before or after).
      When the cost is for a global, set an infinite cost if the overlapping
    segment has a RP distance less or equal to 1 (this is an access segment).
* Bug: In Katana::PowerRailsPlane::Rail::doLayout(), correct computation of
    the segments extension cap.
* New: In Katana::QueryPowerRails::addToPowerRail(), add support for Pad.
* Change: In Katana/PreProcess::protectCagedTerminals(), apply the contraints
    to any turn connected to the first segment of the RoutingPad so the
    perpandicular constraints got propagated to the perpandicular segment...
* Change: In RoutingEvent, cache the "distance to RP" value.
* Change: In RoutingEvent::Key::compare(), sort *first* on distance to
    RoutingPad, then layer depth. If both distance to RoutingPad is null,
    then sort on segment length.
* Change: In RoutingEvent::_processRepair(), try a repack perpandicular with
    perpandiculars first (then with perpandicular last, then give up).
* Change: In SegmentFsm::bindToTrack() and moveToTrack(), set an axis hint
    when creating the insertion event.
* Change: In SegmentFsm::_slackenStrap(), add a step through slacken between
    minimize and maximum slack (wihch directly end up in unimplemented).
* Change: In Session::_addInsertEvent(), add an axis parameter needed when
    the axis of the segment is not the one of the track (case of wide
    segments or non-preferred direction).
* Bug: In Track::_preDestroy(), bad management of the TrackElement reference
    count. Destroy the segment only when reaching zero...
* Bug: In Track::expandFreeIneterval(), forgotten to manage case when there
    is a set of overlaping segments at the "end" of the track, the
    EndIsTrackMax was not set.
* Change: In TrackCost::Compare, increase the cost when an overlaping
    segment is at it's ripup limit. We should try *not* to rip it up if
    we can. Add a dedicated flag "AtRipupLimit".
* Change: In TrackElement, add proxies for isUnbreakable(), new function
    updateTrackSpan().
* New: In TrackFixedSegment CTOR, when a supply wire of METAL2 or above is
    found, make the underlying GCells "GoStraight".
* New: In TrackElement::canDogleg(GCell*), check for already done perpandicular
    dogleg on source/target (reject if so).
2019-07-28 23:20:00 +02:00
Jean-Paul Chaput bc88fe0075 Merge branch 'devel' of ssh://bop-t/users/largo2/git/coriolis into devel 2019-06-04 14:52:21 +02:00
Marie-Minerve Louërat ab517fbfac Typos corrigees dans Hurricane et Python Tutorial 2019-06-04 14:34:20 +02:00
Marie-Minerve Louërat 2bc2fd1583 Typos corrigees dans Users Guide.
Fin de devel_anabatic
2019-06-04 14:32:23 +02:00
Jean-Paul Chaput 8ad910301d In CRLcore, new gauge "msxlib4" for compliance with AMS 350nm (symbolic).
* New: In CRL/etc/symbolic/cmos45/kite.conf, new gauge "msxlib4" for both
    routing and cells. Have only 4 metal layers but with all the same pitches
    and width. Differs from the 45nm compliant where pitches double starting
    from METAL4.
* New: In CRL/etc/symbolic/cmos45/plugins.conf, adjust default parameters for
    the clock tree plugin so they are identical to the one of "cmos" (scaling).
* Change: In CRL/python/helpers/io.py, in catch(), do not set up the script
    path here as it is non-informative.
2019-05-29 13:16:01 +02:00
Jean-Paul Chaput 0df4821806 Full update of the generated documentation for version 2.3 2019-05-27 18:49:51 +02:00
Jean-Paul Chaput 9db39a7b5e Merge branch 'devel_anabatic' of ssh://bop-t/users/largo2/git/coriolis into devel_anabatic
Conflicts:
	documentation/UsersGuide/Installation.rst
2019-05-26 15:52:18 +02:00
Jean-Paul Chaput e00b19d454 In documentation, Update installation instructions. 2019-05-26 15:46:44 +02:00
Jean-Paul Chaput 911095284f Adapt socInstaller to the new SL7 & benchmarks. 2019-05-26 15:41:24 +02:00
Jean-Paul Chaput 4cd0bcb009 Various bug corrections to pass the alliance-check-toolkit reference benchs.
* New: In Isobar::PyCell, export the isRouted() and setRouted() to the
    Python interface.
* Bug: In CRL::Entity::parseEntity(), check that the closing parenthesis
    is the last character of the net name. Issue a more relevant error
    message.
* In Anabatic::NetBuilder::_do_xG() and all other unimplemented methods,
    throw an error if called from a derived classes instead of just
    issuing a message in the debug stream. Avoid later core dumps...
* In Anabatic::NetBuilderHV, implement the builders for GCells with
    one pin. Needed to support chip/corona routing.
* Bug: In Cumulus/plugins/Chip.py, check that coronaCk exists before
    using it.
* New: In Cumulus/plugins/PadsCorona/Side._placePad(), when routing
    a design with symbolic pads, export the chip external "pad"
    connectors to be able to perform a lvx (otherwise cougar do not
    create external nets).
      In Corona._createCoreWire(), set the minimal gap between the pads
    and the corona to 6 pitches. Empirical value to avoid DRC errors
    with symbolic pads (pxlib).
      When successufully done, mark the Corona cell as routed.
* Bug: In Cumulus/plugins/Core2Chip.IoNet, the regex for vectorizet net
    was wrong, it was allowing only one digit in the index.
* Bug: In Cumulus/plugins/Core2Chip.cmos, correct management of
    pad & corona clock nets. Correct connexion between vdde/vddi.
* Bug: In Unicorn/cgt.py, forgot to execute scripts when in text mode.
2019-05-24 23:57:22 +02:00
Marie-Minerve Louërat d641607ac3 Typos corrigees dans Python Tutorial for Hurricane database 2019-05-24 13:55:23 +02:00
Marie-Minerve Louërat 973dedc4a5 Typos corrigees dans les fichiers du User Guide 2019-05-24 13:24:11 +02:00
Marie-Minerve Louërat 10f0f9b55d Ajout Roselyne dans les contributeurs 2019-05-23 17:30:42 +02:00
Marie-Minerve Louërat b78a524e5f Introduction d'une page de garde pour la documentation Coriolis et Python 2019-05-23 15:51:06 +02:00
Jean-Paul Chaput 3fb746fbef Support for mixing real pads & symbolic core. Wrapper around s2r.
* Change: In Hurricane::Error constructors disable the backtrace generation.
    (*very* slow).
* Change: In Hurricane::Library::getHierarchicalname(), more compact
    naming. Remove the name of the root library.
* New: In Hurricane::Net, new type "FUSED", for component with no net.
    More efficient than having one net for each.
* Change: In CellViewer, BreakpointWidget, use Angry Birds icons.
* Change: In CellWidget::State, use the hierarchical name (cached) as key
    to the state. This allow to load two cells with the same name but from
    different libraries in the widget history.
* Change: In PyGraphics, export "isEnabled()" and "isHighDpi()" functions.
* Change: In CRL/etc/symbolic/cmos/plugin.conf, and
    CRL/etc/common/plugin.conf use the physical dimensions converters.
* Change: In CRL/etc/symbolic/cmos/technology.conf, make the GDS layer
    table coherent with the default Alliance cmos.rds.
* New: CRL/python/helpers/io.py, put ErrorMessage new implementation here,
    along with a new ErrorWidget written in PyQt4. It seems finally that
    PyQt4 can be used alongside Coriolis Qt widgets.
      New ErrorMessage.catch() static function to manage all exceptions
    in except clauses.
* Change: In CRL/python/helpers/, no longer use ErrorMessage.wrapPrint(),
    directly print it.
      Rewrite the utilities to display Python stack traces "textStacktrace()"
    and "showStacktrace()".
* Change: In CRL::AllianceFramework, shorten the names of the libraries.
* Change: In CRL::ApParser & CRL::ApDriver, more accurate translation between
    Alliance connectors (C record) and Hurricane::Pin objects. Pin are no
    longer made square but thin and oriented in the connecting direction.
      Use the new fused net for unnamed components.
* New: In CRL::GdsParser, implementation of SREF parsing, i.e. instances.
    Due to the unordered nature of the GDS stream, instances creation are
    delayed until the whole stream has been parsed and only then are they
    created.
      For the sake of reading back Alliance s2r GDS, we assume that any
    TEXT following a boundary is the Net name the boundary (component)
    belongs to.
      Create abutment box for Cells, computed from the bounding box, so
    the Hurricane QuadTree could work properly.
      Make use of the fused net for unnamed components.
* New: In Cumulus/plugins/chip, complete rewrite of the I/O pad management.
    Now we can mix real (foundry) pads and a symbolic core.
      To cleanly support the de-coupling between the real part and the
    symbolic one we introduce a new intermediary hierarchical level, the
    corona. We have now:
      Chip --> Pads + Corona --> Core.
      At chip level (and if we are using real pads) the layout is fully
    real (excepting the corona).
      The Corona contains everything that is symbolic. It has symbolic
    wires extending outward the abutment box to make contact with the
    real wires coming from the pads.
      In the pad ring we can use corners instances (or not), pad spacers
    or directly draw wires between connectors ring pads.
      Provide two flavors: placement only or full place & route.
    WARNING: If routing in a second step, *do not route* the *Chip* but
    the *Corona*.
* Change: In Cumulus/plugins/clocktree, give the modified Cell an
    additional extension of "_cts" (Clock Tree Synthesis) instead of
    "_clocked", to follow the common convention.
* New: In cumulus/plugins/S2R.py, encapsulate call to Alliance S2R and
    reload the translated Cell in the editor.
* New: In cumulus/plugins/core2chip, provide an utility to automatically
    create a chip from a core. To work this plugins must have a basic
    understanding of the pad functionalities which may differs from
    foundry to foundry. So a base class CoreToChip is created, then for
    each supported pad foundry a derived class is added. Currently we
    support AMS c35b4 and Alliance symbolic cmos.
* Bug: In Anabatic::Configuration, read the right configuration parameter
    "anabatic.topRoutinglayer" (Katana), and not the one for Katabatic...
* Change: In Unicorn/cgt.py, process the plugins in alphabetical order
    to ensure a reproductible ordering of the menus...
2019-05-22 14:34:32 +02:00
Jean-Paul Chaput 9bcc81eb7d Tweak FindBoostrap.cmake to detect Qwt under Linux Mint. 2019-05-10 12:12:30 +02:00
Jean-Paul Chaput 1360479eed Switch place in menus between Katana & Kite (Katana becomes the default).
* Change: In Hurricane::CellViewer, reorganisation of the to level menus.
    Add "Misc." and it's two sub-menus "Beta" and "Obsolete".
* Change: In GraphicKiteEngine::addToMenu(), set Kite in the obsolete menu.
* Change: In GraphicKatanaEngine::addToMenu(), set Katana as the standart
    router.
2019-05-10 11:59:21 +02:00
Jean-Paul Chaput 82dc58bf8e Redesign of I/O pads and Corona support to mix real and symbolic.
* Bug: In CRL/etc/symbolic/cmos/plugins.conf, rails dimensions are no
    longer expressed directly in lambda. Must be created using helper.l().
* Change: In CRL::ApParser, slightly more smart management of Pin width.
    Must normalize Pin behavior between Alliance & Hurricane as in
    Alliance they have only one dimension.
* Change: In CRL::LefImport, if a net name end with "!", assume it's a
    global one. Have to check this naming convention.
* Change: In Anabatic::NetBuilderHV::_do_1G_1PinM3() & _do_1G_1PinM2()
    now implemented. Needed for the corona routing support.
* Change: In AnabaticEngine::setupPreRouted(), exclude segments outside
    the abutment box.
* Change: In KatanaEngine::PowerRails, remove the I/O pad support as now
    we route only inside the Corona. So only one vdd/vss/ck are supported.
* New: In cumulus/plugins/ChipPlugin.py, complete rewrite of the chip
    support:
    * Uncouple pad I/O ring whith real cells (foundry) from a symbolic
      core. A new intermediate level "corona" is introduced to handle
      the real/symbolic transition.
    * Ability to explicitly setup position of the pads on the chip side
      in case of uneven distribution.
    * Enable clock tree to be build with 3 metal only (M2 to M4) instead
      of (M2 to M5).
2019-05-10 11:58:05 +02:00
Jean-Paul Chaput ce60ed5a30 In Etesian & Anabatic, use the "anabatic.routingGauge" conf. parameter.
* Change: In Etesian::Configuration CTOR, use the gauge from the
    configuration parameter "anabatic.routinGauge" instead of the default
    one.
* Change: In Anabatic::Configuration CTOR, use the gauge from the
    configuration parameter "anabatic.routinGauge" instead of the default
    one.
2019-05-10 11:54:32 +02:00
Jean-Paul Chaput 43629a6c1c Tweaking Layer & RoutingGauge management. Allow negative track indexes.
* Bug: In Hurricane python module, forgot to add the Segment type.
* Change: In Isobar/layer.getEnclosure() wrapper check and cast the Layer
    argument into BasicLayer.
* Change: In CRL::RoutingGauge::getLayerGauge(Layer*), getLayerType() and
    getLayerDirection() no longer check layer identity based on layer
    mask instead of just Layer* pointer. To allow a unified call wether
    the layer is real or symbolic.
* Change: In CRL::RoutingLayerGauge::getTrackIndex() and getTrackPositon(),
    no longer consider negative indexes as invalid and reset them to
    zero. The check for out of bound index is now left to Anabatic &
    Katana.
* Change: In CRL/RoutingGauge.getRoutingLayer() and getContactLayer(),
    more detailed error message.
* Change: In CRL/RoutingLayerGauge.getTrackIndex() and getTrackPosition(),
    indexes are now signed long instead of unsigned.
2019-05-10 11:52:42 +02:00
Jean-Paul Chaput 2beee8a25c Bug: Compopent creation inside a Collection loop In Cell::flattenNets().
* Bug: In Hurricane::Cell::flattenNets(): Same error again, do not create
    components while iterating over the components Collection.
      Now RoutingPad of top nets are create outside the loop as they must.
2019-05-10 11:48:33 +02:00