Typos corrigees dans Hurricane et Python Tutorial
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@ -26,7 +26,7 @@ hierarchical levels, RoutingPads_ can refer to a deeply buried terminal.
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9.3 HyperNets
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~~~~~~~~~~~~~
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This class is part of the *virtual flattening* mechanisms, it allows to
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This class is part of the *virtual flattening* mechanism, it allows to
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go through all the components of a trans-hierarchical net.
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@ -12,7 +12,7 @@ But, for debugging purpose it may be helpful to run it through the
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interactive layout viewer |cgt|.
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For |cgt| to be able to run your script, you must add to your script
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file a function named :cb:`ScriptMain()`, which takes a dictionnary
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file a function named :cb:`ScriptMain()`, which takes a dictionary
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as sole argument (:cb:`**kw`). The ``kw`` dictionary contains, in
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particular, the CellViewer_ object we are running under with the
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keyword ``editor``. You can then load your cell into the viewer
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@ -71,7 +71,7 @@ function. To be able to see exactly what has just been mofied, we must close the
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UpdateSession_ just before calling the breakpoint and reopen it just after.
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The ``Breakpoint.stop()`` function takes two arguments:
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#. The ``level`` above witch it will be active.
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#. The ``level`` above which it will be active.
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#. An informative message about the purpose of the breakpoint.
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We can create a little function to ease the work:
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@ -19,7 +19,7 @@ In |Hurricane| all kind of set of objects, whether organized in a real container
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like a ``map<>`` (dictionary / ``dict``) or a ``vector<>`` (table / ``list``) or
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an algorithmic walkthrough of the database can be accessed through a Collection_.
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C++ Collections object are exposed in |Python| through the *iterable* protocol,
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C++ Collections objects are exposed in |Python| through the *iterable* protocol,
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allowing to simply write:
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.. code-block:: Python
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@ -83,8 +83,8 @@ the ``getCell()`` call wil be:
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.. note:: It means that if cells with the same name exist in different
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libraries, only the one in the first library will be ever used.
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Be also weary of cell files that may remain in the ``WORK_LIB``,
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they may unexpectedly shadow cells from the libraries.
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Be also aware that cell files that may remain in the ``WORK_LIB``,
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may unexpectedly shadow cells from the libraries.
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.. code-block:: Python
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@ -39,7 +39,7 @@ don't. Thus we summarize below the more important ones:
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Cell_ The model. A Cell does not have terminals, only nets
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flagged as *external*
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Instance_ An instance of a model
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Net_ A grouping of electrically connecteds components
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Net_ A grouping of electrically connected components
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Plug_ A terminal of an instance
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RoutingPad_ A physical connexion (*pin*) to an instance
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=============== =====================================================
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@ -39,7 +39,7 @@ parameters:
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6.2 Creating Nets and connecting to Instances
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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An Instance_ as one Plug_ for each external net of the *master cell*.
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An Instance_ has one Plug_ for each external net of the *master cell*.
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The plug allows to create a **logical** connection bewteen a Net_ of
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``fulladder`` and a net from an Instance_ *master cell*.
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@ -89,7 +89,7 @@ Building the :cb:`a` net of ``fulladder``:
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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For supplies, it may be tedious to connect the Plugs_ of each cell one by one
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(and create a lot of uneeded objects). To avoid that, we may use **Named
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(and create a lot of unneeded objects). To avoid that, we may use **Named
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connections**. If a signal in ``fulladder`` is set to *global*, then it will
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be considered as connected to any signal with the *same name* and *global* in
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the master cell of the instances.
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Binary file not shown.
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@ -9,7 +9,7 @@ Hurricane+Python Tutorial
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Printable version of this document `PythonTutorial.pdf <../../../pdf/main/PythonTutorial.pdf>`_.
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First, a small disclaimer. This tutorial assume that you are already familiar
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First, a small disclaimer. This tutorial assumes that you are already familiar
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with the concepts of |VLSI| designs, such as *netlist*, *layout*, *instances*
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and hierarchical design.
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@ -43,7 +43,7 @@
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|noindent|
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**First, a small disclaimer.** This tutorial assume that you are already familiar
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**First, a small disclaimer.** This tutorial assumes that you are already familiar
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with the concepts of |VLSI| designs, such as *netlist*, *layout*, *instances*
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and hierarchical design.
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