Typos corrigees dans Hurricane et Python Tutorial

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Marie-Minerve Louërat 2019-06-04 14:34:20 +02:00
parent 2bc2fd1583
commit ab517fbfac
8 changed files with 11 additions and 11 deletions

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@ -26,7 +26,7 @@ hierarchical levels, RoutingPads_ can refer to a deeply buried terminal.
9.3 HyperNets
~~~~~~~~~~~~~
This class is part of the *virtual flattening* mechanisms, it allows to
This class is part of the *virtual flattening* mechanism, it allows to
go through all the components of a trans-hierarchical net.

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@ -12,7 +12,7 @@ But, for debugging purpose it may be helpful to run it through the
interactive layout viewer |cgt|.
For |cgt| to be able to run your script, you must add to your script
file a function named :cb:`ScriptMain()`, which takes a dictionnary
file a function named :cb:`ScriptMain()`, which takes a dictionary
as sole argument (:cb:`**kw`). The ``kw`` dictionary contains, in
particular, the CellViewer_ object we are running under with the
keyword ``editor``. You can then load your cell into the viewer
@ -71,7 +71,7 @@ function. To be able to see exactly what has just been mofied, we must close the
UpdateSession_ just before calling the breakpoint and reopen it just after.
The ``Breakpoint.stop()`` function takes two arguments:
#. The ``level`` above witch it will be active.
#. The ``level`` above which it will be active.
#. An informative message about the purpose of the breakpoint.
We can create a little function to ease the work:

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@ -19,7 +19,7 @@ In |Hurricane| all kind of set of objects, whether organized in a real container
like a ``map<>`` (dictionary / ``dict``) or a ``vector<>`` (table / ``list``) or
an algorithmic walkthrough of the database can be accessed through a Collection_.
C++ Collections object are exposed in |Python| through the *iterable* protocol,
C++ Collections objects are exposed in |Python| through the *iterable* protocol,
allowing to simply write:
.. code-block:: Python
@ -83,8 +83,8 @@ the ``getCell()`` call wil be:
.. note:: It means that if cells with the same name exist in different
libraries, only the one in the first library will be ever used.
Be also weary of cell files that may remain in the ``WORK_LIB``,
they may unexpectedly shadow cells from the libraries.
Be also aware that cell files that may remain in the ``WORK_LIB``,
may unexpectedly shadow cells from the libraries.
.. code-block:: Python

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@ -39,7 +39,7 @@ don't. Thus we summarize below the more important ones:
Cell_ The model. A Cell does not have terminals, only nets
flagged as *external*
Instance_ An instance of a model
Net_ A grouping of electrically connecteds components
Net_ A grouping of electrically connected components
Plug_ A terminal of an instance
RoutingPad_ A physical connexion (*pin*) to an instance
=============== =====================================================

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@ -39,7 +39,7 @@ parameters:
6.2 Creating Nets and connecting to Instances
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
An Instance_ as one Plug_ for each external net of the *master cell*.
An Instance_ has one Plug_ for each external net of the *master cell*.
The plug allows to create a **logical** connection bewteen a Net_ of
``fulladder`` and a net from an Instance_ *master cell*.
@ -89,7 +89,7 @@ Building the :cb:`a` net of ``fulladder``:
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
For supplies, it may be tedious to connect the Plugs_ of each cell one by one
(and create a lot of uneeded objects). To avoid that, we may use **Named
(and create a lot of unneeded objects). To avoid that, we may use **Named
connections**. If a signal in ``fulladder`` is set to *global*, then it will
be considered as connected to any signal with the *same name* and *global* in
the master cell of the instances.

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@ -9,7 +9,7 @@ Hurricane+Python Tutorial
Printable version of this document `PythonTutorial.pdf <../../../pdf/main/PythonTutorial.pdf>`_.
First, a small disclaimer. This tutorial assume that you are already familiar
First, a small disclaimer. This tutorial assumes that you are already familiar
with the concepts of |VLSI| designs, such as *netlist*, *layout*, *instances*
and hierarchical design.

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@ -43,7 +43,7 @@
|noindent|
**First, a small disclaimer.** This tutorial assume that you are already familiar
**First, a small disclaimer.** This tutorial assumes that you are already familiar
with the concepts of |VLSI| designs, such as *netlist*, *layout*, *instances*
and hierarchical design.