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coriolis
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Filter out redundant plugs that have no connection inside cell while export Verilog netlist. (#84) 

Co-authored-by: Serge Rabyking <serge.rabyking@chipflow.io>
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lanserge 2023-11-10 13:56:58 +00:00 committed by GitHub
parent 8e5db42aff
commit 500d4446c2
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1 changed files with 21 additions and 0 deletions
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21
crlcore/src/ccore/verilog/VerilogDriver.cpp
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@ -112,6 +112,21 @@ namespace CRL {
return bus; return bus;
} }
static bool _cellHasNetPlug(Cell* cell, Net* net)
{
for(Instance* instance: cell->getInstances()) // go through all cells instances that form our cell
{
for(Plug* plug: instance->getPlugs()) // plugs are connect points of the cells
{
if (plug->getNet() == net)
{
return true;
}
}
}
return false;
}
static void _write_cell(ofstream &out, Cell* cell) static void _write_cell(ofstream &out, Cell* cell)
{ {
out << std::endl; out << std::endl;
@ -309,6 +324,12 @@ namespace CRL {
{ {
continue; continue;
} }
if (!instance->isTerminalNetlist()&&
!_cellHasNetPlug(instance->getMasterCell(), net))
{
// the plug is redundant and actually has no connection inside cell
continue;
}
// insert in sorted order // insert in sorted order
auto it = std::lower_bound(conns.begin(), conns.end(), plug, auto it = std::lower_bound(conns.begin(), conns.end(), plug,
[](Plug* lhs, Plug* rhs) -> bool [](Plug* lhs, Plug* rhs) -> bool