diff --git a/crlcore/src/ccore/verilog/VerilogDriver.cpp b/crlcore/src/ccore/verilog/VerilogDriver.cpp
index c44da8da..58442f8f 100644
--- a/crlcore/src/ccore/verilog/VerilogDriver.cpp
+++ b/crlcore/src/ccore/verilog/VerilogDriver.cpp
@@ -112,6 +112,21 @@ namespace CRL {
     return bus;
   }
 
+  static bool _cellHasNetPlug(Cell* cell, Net* net)
+  {
+    for(Instance* instance: cell->getInstances()) // go through all cells instances that form our cell
+    {
+      for(Plug* plug: instance->getPlugs()) // plugs are connect points of the cells
+      {
+        if (plug->getNet() == net)
+        {
+          return true;
+        }
+      }
+    }
+    return false;
+  }
+
   static void _write_cell(ofstream &out, Cell* cell)
   {
     out << std::endl;
@@ -309,6 +324,12 @@ namespace CRL {
         {
           continue;
         }
+        if (!instance->isTerminalNetlist()&&
+            !_cellHasNetPlug(instance->getMasterCell(), net))
+        {
+          // the plug is redundant and actually has no connection inside cell
+          continue;
+        }
         // insert in sorted order
         auto it = std::lower_bound(conns.begin(), conns.end(), plug,
                      [](Plug* lhs, Plug* rhs) -> bool