From 500d4446c2a71a79b8e110166f37290220142186 Mon Sep 17 00:00:00 2001 From: lanserge Date: Fri, 10 Nov 2023 13:56:58 +0000 Subject: [PATCH] Filter out redundant plugs that have no connection inside cell while export Verilog netlist. (#84) Co-authored-by: Serge Rabyking --- crlcore/src/ccore/verilog/VerilogDriver.cpp | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/crlcore/src/ccore/verilog/VerilogDriver.cpp b/crlcore/src/ccore/verilog/VerilogDriver.cpp index c44da8da..58442f8f 100644 --- a/crlcore/src/ccore/verilog/VerilogDriver.cpp +++ b/crlcore/src/ccore/verilog/VerilogDriver.cpp @@ -112,6 +112,21 @@ namespace CRL { return bus; } + static bool _cellHasNetPlug(Cell* cell, Net* net) + { + for(Instance* instance: cell->getInstances()) // go through all cells instances that form our cell + { + for(Plug* plug: instance->getPlugs()) // plugs are connect points of the cells + { + if (plug->getNet() == net) + { + return true; + } + } + } + return false; + } + static void _write_cell(ofstream &out, Cell* cell) { out << std::endl; @@ -309,6 +324,12 @@ namespace CRL { { continue; } + if (!instance->isTerminalNetlist()&& + !_cellHasNetPlug(instance->getMasterCell(), net)) + { + // the plug is redundant and actually has no connection inside cell + continue; + } // insert in sorted order auto it = std::lower_bound(conns.begin(), conns.end(), plug, [](Plug* lhs, Plug* rhs) -> bool