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caravel
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Tim Edwards f28950695d Made adjustments to the padframe routing to move all routes closer 
to the padframe and free up more space for routing in the chip
interior.
 		2021-11-15 11:52:08 -05:00
def [DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz 2021-11-15 15:50:43 +02:00
doc Updated the floorplan. 2021-11-10 12:21:22 -05:00
gds [DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz 2021-11-15 15:50:43 +02:00
lef [DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz 2021-11-15 15:50:43 +02:00
mag Made adjustments to the padframe routing to move all routes closer 2021-11-15 11:52:08 -05:00
maglef [DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz 2021-11-15 15:50:43 +02:00
openlane [DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz 2021-11-15 15:50:43 +02:00
scripts Finished first draft of the gen_gpio_defaults.py script, which now 2021-11-07 21:51:00 -05:00
signoff [DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz 2021-11-15 15:50:43 +02:00
spi/lvs [DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz 2021-11-15 15:50:43 +02:00
verilog [DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz 2021-11-15 15:50:43 +02:00
xschem Added the files for the simple_por block design, and placed the latest 2021-11-15 10:34:52 -05:00
Makefile Modified the Makefile so that "make lvs-gds-" works better (maybe 2021-11-11 08:48:14 -05:00
README.md Update README.md 2021-10-12 10:28:29 -07:00

README.md

caravel_openframe

This is an ongoing investigation regarding the creation of a new openframe based version of Caravel.

Link to schedule: https://plan.tomsplanner.com/public/caravel-openframe