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riscv
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caravel
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e93c6cc16b
caravel
/
verilog
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Kareem Farid
8e02ea79d8
fix wrong cell name
...
`sky130_fd_sc_hd__dlygate4sd2` is called `sky130_fd_sc_hd__dlygate4sd2_1`
2022-03-22 17:02:36 +02:00
..
dv
Added a testbench that exercises the SRAM 2nd (read-only) port, as
2021-12-29 11:24:17 -05:00
gl
Corrected the gen_gpio_defaults.py script so that it behaves
2021-12-29 15:42:41 -05:00
rtl
fix wrong cell name
2022-03-22 17:02:36 +02:00
stubs
[DATA] Add spare_logic_block
2021-11-24 20:36:23 +02:00