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caravel
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manarabdelaty d7ae2e1ac1 [RTL] Move inverter from top level to HK 
- fixed clock connection to the digital_pll and caravel_clocking
- renamed power pins of the HK/caravel_clocking to VPWR/VGND
 		2021-11-16 13:59:17 +02:00
def [DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz 2021-11-15 15:50:43 +02:00
doc Updated the floorplan. 2021-11-10 12:21:22 -05:00
gds Add gds view for chip_io 2021-11-15 23:02:01 +02:00
lef Add gds view for chip_io 2021-11-15 23:02:01 +02:00
mag Corrected chip_io and chip_io_alt layouts to restore the accidentally 2021-11-15 17:13:43 -05:00
maglef [DATA] Add gds/lef/maglef/gl views for the user_id_programming block 2021-11-15 18:17:32 +02:00
openlane [DATA] Add gds/lef/maglef/gl views for the user_id_programming block 2021-11-15 18:17:32 +02:00
scripts Modified the set_user_id script so that if it happens to be run on 2021-11-15 16:41:04 -05:00
signoff [DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz 2021-11-15 15:50:43 +02:00
spi/lvs [DATA] Add gds/lef/maglef/gl views for the user_id_programming block 2021-11-15 18:17:32 +02:00
verilog [RTL] Move inverter from top level to HK 2021-11-16 13:59:17 +02:00
xschem Added the files for the simple_por block design, and placed the latest 2021-11-15 10:34:52 -05:00
Makefile Modified the Makefile so that "make lvs-gds-" works better (maybe 2021-11-11 08:48:14 -05:00
README.md Update README.md 2021-10-12 10:28:29 -07:00
info.yaml Modified the set_user_id script so that if it happens to be run on 2021-11-15 16:41:04 -05:00

README.md

caravel_openframe

This is an ongoing investigation regarding the creation of a new openframe based version of Caravel.

Link to schedule: https://plan.tomsplanner.com/public/caravel-openframe