mirror of https://github.com/efabless/caravel.git
1706 lines
40 KiB
Verilog
1706 lines
40 KiB
Verilog
module gpio_control_block (mgmt_gpio_in,
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mgmt_gpio_oeb,
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mgmt_gpio_out,
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one,
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pad_gpio_ana_en,
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pad_gpio_ana_pol,
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pad_gpio_ana_sel,
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pad_gpio_holdover,
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pad_gpio_ib_mode_sel,
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pad_gpio_in,
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pad_gpio_inenb,
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pad_gpio_out,
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pad_gpio_outenb,
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pad_gpio_slow_sel,
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pad_gpio_vtrip_sel,
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resetn,
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resetn_out,
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serial_clock,
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serial_clock_out,
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serial_data_in,
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serial_data_out,
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serial_load,
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serial_load_out,
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user_gpio_in,
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user_gpio_oeb,
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user_gpio_out,
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vccd,
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vccd1,
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vssd,
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vssd1,
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zero,
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gpio_defaults,
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pad_gpio_dm);
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output mgmt_gpio_in;
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input mgmt_gpio_oeb;
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input mgmt_gpio_out;
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output one;
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output pad_gpio_ana_en;
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output pad_gpio_ana_pol;
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output pad_gpio_ana_sel;
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output pad_gpio_holdover;
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output pad_gpio_ib_mode_sel;
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input pad_gpio_in;
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output pad_gpio_inenb;
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output pad_gpio_out;
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output pad_gpio_outenb;
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output pad_gpio_slow_sel;
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output pad_gpio_vtrip_sel;
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input resetn;
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output resetn_out;
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input serial_clock;
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output serial_clock_out;
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input serial_data_in;
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output serial_data_out;
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input serial_load;
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output serial_load_out;
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output user_gpio_in;
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input user_gpio_oeb;
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input user_gpio_out;
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input vccd;
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input vccd1;
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input vssd;
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input vssd1;
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output zero;
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input [12:0] gpio_defaults;
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output [2:0] pad_gpio_dm;
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wire _000_;
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wire _001_;
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wire _002_;
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wire _003_;
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wire _004_;
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wire _005_;
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wire _006_;
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wire _007_;
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wire _008_;
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wire _009_;
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wire _010_;
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wire _011_;
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wire _012_;
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wire _013_;
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wire _014_;
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wire _015_;
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wire _016_;
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wire _017_;
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wire _018_;
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wire _019_;
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wire _020_;
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wire _021_;
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wire _022_;
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wire _023_;
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wire _024_;
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wire _025_;
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wire _026_;
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wire _027_;
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wire _042_;
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wire _043_;
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wire _044_;
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wire _045_;
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wire _046_;
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wire _047_;
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wire _048_;
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wire _049_;
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wire _050_;
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wire _051_;
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wire _052_;
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wire _053_;
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wire _054_;
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wire _055_;
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wire _056_;
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wire _057_;
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wire clknet_0_serial_clock;
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wire clknet_0_serial_load;
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wire clknet_1_0__leaf_serial_clock;
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wire clknet_1_0__leaf_serial_load;
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wire clknet_1_1__leaf_serial_clock;
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wire clknet_1_1__leaf_serial_load;
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wire gpio_logic1;
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wire gpio_outenb;
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wire mgmt_ena;
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wire net1;
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wire net10;
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wire net11;
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wire net12;
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wire net13;
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wire net14;
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wire net15;
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wire net16;
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wire net17;
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wire net18;
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wire net19;
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wire net2;
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wire net20;
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wire net21;
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wire net22;
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wire net23;
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wire net24;
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wire net25;
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wire net26;
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wire net27;
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wire net3;
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wire net4;
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wire net5;
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wire net6;
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wire net7;
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wire net8;
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wire net9;
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wire \shift_register[0] ;
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wire \shift_register[10] ;
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wire \shift_register[11] ;
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wire \shift_register[12] ;
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wire \shift_register[1] ;
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wire \shift_register[2] ;
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wire \shift_register[3] ;
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wire \shift_register[4] ;
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wire \shift_register[5] ;
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wire \shift_register[6] ;
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wire \shift_register[7] ;
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wire \shift_register[8] ;
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wire \shift_register[9] ;
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sky130_fd_sc_hd__diode_2 ANTENNA__058__A (.DIODE(pad_gpio_in),
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__061__A_N (.DIODE(pad_gpio_inenb),
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__062__B (.DIODE(user_gpio_oeb),
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__063__A2 (.DIODE(mgmt_gpio_oeb),
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__064__A_N (.DIODE(pad_gpio_dm[2]),
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__064__C (.DIODE(mgmt_gpio_oeb),
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__065__A0 (.DIODE(mgmt_gpio_out),
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__066__A0 (.DIODE(user_gpio_out),
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__067__A (.DIODE(resetn),
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__067__B (.DIODE(gpio_defaults[0]),
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__068__A_N (.DIODE(resetn),
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__068__B (.DIODE(gpio_defaults[0]),
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__069__A (.DIODE(resetn),
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__069__B (.DIODE(gpio_defaults[2]),
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__070__A_N (.DIODE(resetn),
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__070__B (.DIODE(gpio_defaults[2]),
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__071__A (.DIODE(resetn),
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__071__B (.DIODE(gpio_defaults[8]),
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__072__A_N (.DIODE(resetn),
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__072__B (.DIODE(gpio_defaults[8]),
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__073__A (.DIODE(resetn),
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__073__B (.DIODE(gpio_defaults[9]),
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__074__A_N (.DIODE(resetn),
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__074__B (.DIODE(gpio_defaults[9]),
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__075__A (.DIODE(resetn),
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__075__B (.DIODE(gpio_defaults[3]),
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__076__A_N (.DIODE(resetn),
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__076__B (.DIODE(gpio_defaults[3]),
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__077__A (.DIODE(resetn),
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__077__B (.DIODE(gpio_defaults[4]),
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__078__A_N (.DIODE(resetn),
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__078__B (.DIODE(gpio_defaults[4]),
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__079__A (.DIODE(resetn),
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__079__B (.DIODE(gpio_defaults[1]),
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__080__A_N (.DIODE(resetn),
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__080__B (.DIODE(gpio_defaults[1]),
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__081__A (.DIODE(resetn),
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__081__B (.DIODE(gpio_defaults[10]),
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__082__A_N (.DIODE(resetn),
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__082__B (.DIODE(gpio_defaults[10]),
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__083__A (.DIODE(resetn),
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__083__B (.DIODE(gpio_defaults[11]),
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__084__A_N (.DIODE(resetn),
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__084__B (.DIODE(gpio_defaults[11]),
|
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__085__A (.DIODE(resetn),
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__085__B (.DIODE(gpio_defaults[12]),
|
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__086__A_N (.DIODE(resetn),
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__086__B (.DIODE(gpio_defaults[12]),
|
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__087__A (.DIODE(resetn),
|
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__087__B (.DIODE(gpio_defaults[5]),
|
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__088__A_N (.DIODE(resetn),
|
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__088__B (.DIODE(gpio_defaults[5]),
|
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__089__A (.DIODE(resetn),
|
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__089__B (.DIODE(gpio_defaults[6]),
|
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.VGND(vssd),
|
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.VNB(vssd),
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__090__A_N (.DIODE(resetn),
|
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.VGND(vssd),
|
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.VNB(vssd),
|
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.VPB(vccd),
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.VPWR(vccd));
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sky130_fd_sc_hd__diode_2 ANTENNA__090__B (.DIODE(gpio_defaults[6]),
|
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.VGND(vssd),
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.VNB(vssd),
|
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.VPB(vccd),
|
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.VPWR(vccd));
|
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sky130_fd_sc_hd__diode_2 ANTENNA__091__A (.DIODE(resetn),
|
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.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__diode_2 ANTENNA__091__B (.DIODE(gpio_defaults[7]),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__diode_2 ANTENNA__092__A_N (.DIODE(resetn),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__diode_2 ANTENNA__092__B (.DIODE(gpio_defaults[7]),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__diode_2 ANTENNA__118__D (.DIODE(serial_data_in),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__diode_2 ANTENNA__118__RESET_B (.DIODE(resetn),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__diode_2 ANTENNA__119__RESET_B (.DIODE(resetn),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__diode_2 ANTENNA__120__RESET_B (.DIODE(resetn),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__diode_2 ANTENNA__121__RESET_B (.DIODE(resetn),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__diode_2 ANTENNA__122__RESET_B (.DIODE(resetn),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__diode_2 ANTENNA__123__RESET_B (.DIODE(resetn),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__diode_2 ANTENNA__124__RESET_B (.DIODE(resetn),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__diode_2 ANTENNA__125__RESET_B (.DIODE(resetn),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__diode_2 ANTENNA__126__RESET_B (.DIODE(resetn),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__diode_2 ANTENNA__127__RESET_B (.DIODE(resetn),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__diode_2 ANTENNA__128__RESET_B (.DIODE(resetn),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__diode_2 ANTENNA__129__RESET_B (.DIODE(resetn),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__diode_2 ANTENNA__130__RESET_B (.DIODE(resetn),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__diode_2 ANTENNA__131__RESET_B (.DIODE(resetn),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__diode_2 ANTENNA__132__A (.DIODE(resetn),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__diode_2 ANTENNA__135__A (.DIODE(pad_gpio_in),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__diode_2 ANTENNA_clkbuf_0_serial_clock_A (.DIODE(serial_clock),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__diode_2 ANTENNA_clkbuf_0_serial_load_A (.DIODE(serial_load),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__fill_1 FILLER_0_50 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_12 FILLER_0_52 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_12 FILLER_0_64 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_3 FILLER_0_76 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_12 FILLER_0_80 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__fill_1 FILLER_10_27 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_3 FILLER_10_3 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__fill_1 FILLER_10_44 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__fill_1 FILLER_10_76 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__fill_1 FILLER_11_15 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_12 FILLER_11_3 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__fill_1 FILLER_11_48 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_4 FILLER_12_15 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_12 FILLER_12_3 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_3 FILLER_13_3 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__fill_1 FILLER_13_35 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_12 FILLER_14_3 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__fill_1 FILLER_14_38 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__fill_1 FILLER_14_83 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__fill_1 FILLER_14_85 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__fill_2 FILLER_15_3 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__fill_1 FILLER_15_65 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_4 FILLER_16_3 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__fill_1 FILLER_17_11 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_8 FILLER_17_3 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__fill_1 FILLER_17_72 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_6 FILLER_18_15 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__fill_2 FILLER_18_24 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_12 FILLER_18_3 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__fill_2 FILLER_18_44 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_4 FILLER_18_48 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__fill_1 FILLER_18_52 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__fill_1 FILLER_18_61 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_3 FILLER_18_66 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__fill_1 FILLER_18_71 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__fill_1 FILLER_18_79 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__fill_1 FILLER_18_85 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_12 FILLER_1_56 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__fill_1 FILLER_1_68 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_4 FILLER_1_71 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__fill_1 FILLER_1_75 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__fill_1 FILLER_1_78 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__fill_1 FILLER_1_82 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__fill_1 FILLER_2_40 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__fill_1 FILLER_2_44 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__fill_1 FILLER_2_70 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__fill_1 FILLER_2_83 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__fill_1 FILLER_3_39 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__fill_1 FILLER_3_93 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__fill_1 FILLER_6_50 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__fill_1 FILLER_6_60 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__fill_1 FILLER_7_76 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__fill_1 FILLER_7_93 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__fill_1 FILLER_8_29 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__fill_2 FILLER_8_3 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_8 FILLER_9_3 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_3 PHY_0 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_3 PHY_1 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_3 PHY_10 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_3 PHY_11 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_3 PHY_12 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_3 PHY_13 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_3 PHY_14 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_3 PHY_15 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_3 PHY_16 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_3 PHY_17 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_3 PHY_18 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_3 PHY_19 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_3 PHY_2 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_3 PHY_20 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_3 PHY_21 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_3 PHY_22 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_3 PHY_23 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_3 PHY_24 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_3 PHY_25 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_3 PHY_26 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_3 PHY_27 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_3 PHY_28 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_3 PHY_29 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_3 PHY_3 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_3 PHY_30 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_3 PHY_31 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_3 PHY_32 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_3 PHY_33 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_3 PHY_34 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_3 PHY_35 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_3 PHY_36 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_3 PHY_37 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_3 PHY_4 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_3 PHY_5 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_3 PHY_6 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_3 PHY_7 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_3 PHY_8 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__decap_3 PHY_9 (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_38 (.VGND(vssd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_39 (.VGND(vssd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_40 (.VGND(vssd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_41 (.VGND(vssd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_42 (.VGND(vssd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_43 (.VGND(vssd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_44 (.VGND(vssd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_45 (.VGND(vssd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_46 (.VGND(vssd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_47 (.VGND(vssd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_48 (.VGND(vssd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_49 (.VGND(vssd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_50 (.VGND(vssd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_51 (.VGND(vssd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_52 (.VGND(vssd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_53 (.VGND(vssd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_54 (.VGND(vssd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_55 (.VGND(vssd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_56 (.VGND(vssd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_57 (.VGND(vssd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_58 (.VGND(vssd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_59 (.VGND(vssd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_60 (.VGND(vssd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_61 (.VGND(vssd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_62 (.VGND(vssd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_63 (.VGND(vssd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_64 (.VGND(vssd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_65 (.VGND(vssd),
|
|
.VPWR(vccd));
|
|
sky130_fd_sc_hd__inv_2 _058_ (.A(pad_gpio_in),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Y(_001_));
|
|
sky130_fd_sc_hd__inv_2 _059__1 (.A(clknet_1_1__leaf_serial_load),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Y(net1));
|
|
sky130_fd_sc_hd__inv_2 _060__14 (.A(clknet_1_1__leaf_serial_clock),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Y(net14));
|
|
sky130_fd_sc_hd__nand2b_2 _061_ (.A_N(pad_gpio_inenb),
|
|
.B(gpio_outenb),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Y(_045_));
|
|
sky130_fd_sc_hd__and2b_2 _062_ (.A_N(mgmt_ena),
|
|
.B(user_gpio_oeb),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.X(_042_));
|
|
sky130_fd_sc_hd__a31o_2 _063_ (.A1(gpio_outenb),
|
|
.A2(mgmt_gpio_oeb),
|
|
.A3(mgmt_ena),
|
|
.B1(_042_),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.X(pad_gpio_outenb));
|
|
sky130_fd_sc_hd__and3b_2 _064_ (.A_N(pad_gpio_dm[2]),
|
|
.B(pad_gpio_dm[1]),
|
|
.C(mgmt_gpio_oeb),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.X(_043_));
|
|
sky130_fd_sc_hd__mux2_1 _065_ (.A0(mgmt_gpio_out),
|
|
.A1(_000_),
|
|
.S(_043_),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.X(_044_));
|
|
sky130_fd_sc_hd__mux2_1 _066_ (.A0(user_gpio_out),
|
|
.A1(_044_),
|
|
.S(mgmt_ena),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.X(pad_gpio_out));
|
|
sky130_fd_sc_hd__or2_2 _067_ (.A(resetn),
|
|
.B(gpio_defaults[0]),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.X(_002_));
|
|
sky130_fd_sc_hd__nand2b_2 _068_ (.A_N(resetn),
|
|
.B(gpio_defaults[0]),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Y(_003_));
|
|
sky130_fd_sc_hd__or2_2 _069_ (.A(resetn),
|
|
.B(gpio_defaults[2]),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.X(_004_));
|
|
sky130_fd_sc_hd__nand2b_2 _070_ (.A_N(resetn),
|
|
.B(gpio_defaults[2]),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Y(_005_));
|
|
sky130_fd_sc_hd__or2_2 _071_ (.A(resetn),
|
|
.B(gpio_defaults[8]),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.X(_006_));
|
|
sky130_fd_sc_hd__nand2b_2 _072_ (.A_N(resetn),
|
|
.B(gpio_defaults[8]),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Y(_007_));
|
|
sky130_fd_sc_hd__or2_2 _073_ (.A(resetn),
|
|
.B(gpio_defaults[9]),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.X(_008_));
|
|
sky130_fd_sc_hd__nand2b_2 _074_ (.A_N(resetn),
|
|
.B(gpio_defaults[9]),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Y(_009_));
|
|
sky130_fd_sc_hd__or2_2 _075_ (.A(resetn),
|
|
.B(gpio_defaults[3]),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.X(_010_));
|
|
sky130_fd_sc_hd__nand2b_2 _076_ (.A_N(resetn),
|
|
.B(gpio_defaults[3]),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Y(_011_));
|
|
sky130_fd_sc_hd__or2_2 _077_ (.A(resetn),
|
|
.B(gpio_defaults[4]),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.X(_012_));
|
|
sky130_fd_sc_hd__nand2b_2 _078_ (.A_N(resetn),
|
|
.B(gpio_defaults[4]),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Y(_013_));
|
|
sky130_fd_sc_hd__or2_2 _079_ (.A(resetn),
|
|
.B(gpio_defaults[1]),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.X(_014_));
|
|
sky130_fd_sc_hd__nand2b_2 _080_ (.A_N(resetn),
|
|
.B(gpio_defaults[1]),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Y(_015_));
|
|
sky130_fd_sc_hd__or2_2 _081_ (.A(resetn),
|
|
.B(gpio_defaults[10]),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.X(_016_));
|
|
sky130_fd_sc_hd__nand2b_2 _082_ (.A_N(resetn),
|
|
.B(gpio_defaults[10]),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Y(_017_));
|
|
sky130_fd_sc_hd__or2_2 _083_ (.A(resetn),
|
|
.B(gpio_defaults[11]),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.X(_018_));
|
|
sky130_fd_sc_hd__nand2b_2 _084_ (.A_N(resetn),
|
|
.B(gpio_defaults[11]),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Y(_019_));
|
|
sky130_fd_sc_hd__or2_2 _085_ (.A(resetn),
|
|
.B(gpio_defaults[12]),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.X(_020_));
|
|
sky130_fd_sc_hd__nand2b_2 _086_ (.A_N(resetn),
|
|
.B(gpio_defaults[12]),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Y(_021_));
|
|
sky130_fd_sc_hd__or2_2 _087_ (.A(resetn),
|
|
.B(gpio_defaults[5]),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.X(_022_));
|
|
sky130_fd_sc_hd__nand2b_2 _088_ (.A_N(resetn),
|
|
.B(gpio_defaults[5]),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Y(_023_));
|
|
sky130_fd_sc_hd__or2_2 _089_ (.A(resetn),
|
|
.B(gpio_defaults[6]),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.X(_024_));
|
|
sky130_fd_sc_hd__nand2b_2 _090_ (.A_N(resetn),
|
|
.B(gpio_defaults[6]),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Y(_025_));
|
|
sky130_fd_sc_hd__or2_2 _091_ (.A(resetn),
|
|
.B(gpio_defaults[7]),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.X(_026_));
|
|
sky130_fd_sc_hd__nand2b_2 _092_ (.A_N(resetn),
|
|
.B(gpio_defaults[7]),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Y(_027_));
|
|
sky130_fd_sc_hd__inv_2 _093__2 (.A(clknet_1_1__leaf_serial_load),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Y(net2));
|
|
sky130_fd_sc_hd__inv_2 _094__3 (.A(clknet_1_1__leaf_serial_load),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Y(net3));
|
|
sky130_fd_sc_hd__inv_2 _095__4 (.A(clknet_1_1__leaf_serial_load),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Y(net4));
|
|
sky130_fd_sc_hd__inv_2 _096__5 (.A(clknet_1_1__leaf_serial_load),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Y(net5));
|
|
sky130_fd_sc_hd__inv_2 _097__6 (.A(clknet_1_0__leaf_serial_load),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Y(net6));
|
|
sky130_fd_sc_hd__inv_2 _098__7 (.A(clknet_1_1__leaf_serial_load),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Y(net7));
|
|
sky130_fd_sc_hd__inv_2 _099__8 (.A(clknet_1_0__leaf_serial_load),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Y(net8));
|
|
sky130_fd_sc_hd__inv_2 _100__9 (.A(clknet_1_0__leaf_serial_load),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Y(net9));
|
|
sky130_fd_sc_hd__inv_2 _101__10 (.A(clknet_1_1__leaf_serial_load),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Y(net10));
|
|
sky130_fd_sc_hd__inv_2 _102__11 (.A(clknet_1_0__leaf_serial_load),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Y(net11));
|
|
sky130_fd_sc_hd__inv_2 _103__12 (.A(clknet_1_0__leaf_serial_load),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Y(net12));
|
|
sky130_fd_sc_hd__inv_2 _104__13 (.A(clknet_1_0__leaf_serial_load),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Y(net13));
|
|
sky130_fd_sc_hd__dfbbn_2 _105_ (.CLK_N(net1),
|
|
.D(net20),
|
|
.RESET_B(_002_),
|
|
.SET_B(_003_),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Q(mgmt_ena),
|
|
.Q_N(_056_));
|
|
sky130_fd_sc_hd__dfbbn_2 _106_ (.CLK_N(net2),
|
|
.D(net17),
|
|
.RESET_B(_004_),
|
|
.SET_B(_005_),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Q(pad_gpio_holdover),
|
|
.Q_N(_055_));
|
|
sky130_fd_sc_hd__dfbbn_2 _107_ (.CLK_N(net3),
|
|
.D(net21),
|
|
.RESET_B(_006_),
|
|
.SET_B(_007_),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Q(pad_gpio_slow_sel),
|
|
.Q_N(_054_));
|
|
sky130_fd_sc_hd__dfbbn_2 _108_ (.CLK_N(net4),
|
|
.D(net16),
|
|
.RESET_B(_008_),
|
|
.SET_B(_009_),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Q(pad_gpio_vtrip_sel),
|
|
.Q_N(_053_));
|
|
sky130_fd_sc_hd__dfbbn_2 _109_ (.CLK_N(net5),
|
|
.D(net18),
|
|
.RESET_B(_010_),
|
|
.SET_B(_011_),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Q(pad_gpio_inenb),
|
|
.Q_N(_052_));
|
|
sky130_fd_sc_hd__dfbbn_2 _110_ (.CLK_N(net6),
|
|
.D(net23),
|
|
.RESET_B(_012_),
|
|
.SET_B(_013_),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Q(pad_gpio_ib_mode_sel),
|
|
.Q_N(_051_));
|
|
sky130_fd_sc_hd__dfbbn_2 _111_ (.CLK_N(net7),
|
|
.D(net19),
|
|
.RESET_B(_014_),
|
|
.SET_B(_015_),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Q(gpio_outenb),
|
|
.Q_N(_050_));
|
|
sky130_fd_sc_hd__dfbbn_2 _112_ (.CLK_N(net8),
|
|
.D(net22),
|
|
.RESET_B(_016_),
|
|
.SET_B(_017_),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Q(pad_gpio_dm[0]),
|
|
.Q_N(_000_));
|
|
sky130_fd_sc_hd__dfbbn_2 _113_ (.CLK_N(net9),
|
|
.D(net27),
|
|
.RESET_B(_018_),
|
|
.SET_B(_019_),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Q(pad_gpio_dm[1]),
|
|
.Q_N(_049_));
|
|
sky130_fd_sc_hd__dfbbn_2 _114_ (.CLK_N(net10),
|
|
.D(net15),
|
|
.RESET_B(_020_),
|
|
.SET_B(_021_),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Q(pad_gpio_dm[2]),
|
|
.Q_N(_048_));
|
|
sky130_fd_sc_hd__dfbbn_2 _115_ (.CLK_N(net11),
|
|
.D(net26),
|
|
.RESET_B(_022_),
|
|
.SET_B(_023_),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Q(pad_gpio_ana_en),
|
|
.Q_N(_047_));
|
|
sky130_fd_sc_hd__dfbbn_2 _116_ (.CLK_N(net12),
|
|
.D(net24),
|
|
.RESET_B(_024_),
|
|
.SET_B(_025_),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Q(pad_gpio_ana_sel),
|
|
.Q_N(_046_));
|
|
sky130_fd_sc_hd__dfbbn_2 _117_ (.CLK_N(net13),
|
|
.D(net25),
|
|
.RESET_B(_026_),
|
|
.SET_B(_027_),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Q(pad_gpio_ana_pol),
|
|
.Q_N(_057_));
|
|
sky130_fd_sc_hd__dfrtp_2 _118_ (.CLK(clknet_1_1__leaf_serial_clock),
|
|
.D(serial_data_in),
|
|
.RESET_B(resetn),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Q(\shift_register[0] ));
|
|
sky130_fd_sc_hd__dfrtp_2 _119_ (.CLK(clknet_1_0__leaf_serial_clock),
|
|
.D(net20),
|
|
.RESET_B(resetn),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Q(\shift_register[1] ));
|
|
sky130_fd_sc_hd__dfrtp_2 _120_ (.CLK(clknet_1_0__leaf_serial_clock),
|
|
.D(net19),
|
|
.RESET_B(resetn),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Q(\shift_register[2] ));
|
|
sky130_fd_sc_hd__dfrtp_2 _121_ (.CLK(clknet_1_0__leaf_serial_clock),
|
|
.D(net17),
|
|
.RESET_B(resetn),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Q(\shift_register[3] ));
|
|
sky130_fd_sc_hd__dfrtp_2 _122_ (.CLK(clknet_1_0__leaf_serial_clock),
|
|
.D(net18),
|
|
.RESET_B(resetn),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Q(\shift_register[4] ));
|
|
sky130_fd_sc_hd__dfrtp_2 _123_ (.CLK(clknet_1_0__leaf_serial_clock),
|
|
.D(net23),
|
|
.RESET_B(resetn),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Q(\shift_register[5] ));
|
|
sky130_fd_sc_hd__dfrtp_2 _124_ (.CLK(clknet_1_0__leaf_serial_clock),
|
|
.D(net26),
|
|
.RESET_B(resetn),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Q(\shift_register[6] ));
|
|
sky130_fd_sc_hd__dfrtp_2 _125_ (.CLK(clknet_1_0__leaf_serial_clock),
|
|
.D(net24),
|
|
.RESET_B(resetn),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Q(\shift_register[7] ));
|
|
sky130_fd_sc_hd__dfrtp_2 _126_ (.CLK(clknet_1_0__leaf_serial_clock),
|
|
.D(net25),
|
|
.RESET_B(resetn),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Q(\shift_register[8] ));
|
|
sky130_fd_sc_hd__dfrtp_2 _127_ (.CLK(clknet_1_1__leaf_serial_clock),
|
|
.D(net21),
|
|
.RESET_B(resetn),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Q(\shift_register[9] ));
|
|
sky130_fd_sc_hd__dfrtp_2 _128_ (.CLK(clknet_1_1__leaf_serial_clock),
|
|
.D(net16),
|
|
.RESET_B(resetn),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Q(\shift_register[10] ));
|
|
sky130_fd_sc_hd__dfrtp_2 _129_ (.CLK(clknet_1_1__leaf_serial_clock),
|
|
.D(net22),
|
|
.RESET_B(resetn),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Q(\shift_register[11] ));
|
|
sky130_fd_sc_hd__dfrtp_2 _130_ (.CLK(clknet_1_1__leaf_serial_clock),
|
|
.D(net27),
|
|
.RESET_B(resetn),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Q(\shift_register[12] ));
|
|
sky130_fd_sc_hd__dfrtp_2 _131_ (.CLK(net14),
|
|
.D(\shift_register[12] ),
|
|
.RESET_B(resetn),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Q(serial_data_out));
|
|
sky130_fd_sc_hd__buf_2 _132_ (.A(resetn),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.X(resetn_out));
|
|
sky130_fd_sc_hd__buf_2 _133_ (.A(clknet_1_1__leaf_serial_clock),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.X(serial_clock_out));
|
|
sky130_fd_sc_hd__buf_2 _134_ (.A(clknet_1_1__leaf_serial_load),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.X(serial_load_out));
|
|
sky130_fd_sc_hd__ebufn_2 _135_ (.A(pad_gpio_in),
|
|
.TE_B(_045_),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Z(mgmt_gpio_in));
|
|
sky130_fd_sc_hd__clkbuf_16 clkbuf_0_serial_clock (.A(serial_clock),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.X(clknet_0_serial_clock));
|
|
sky130_fd_sc_hd__clkbuf_16 clkbuf_0_serial_load (.A(serial_load),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.X(clknet_0_serial_load));
|
|
sky130_fd_sc_hd__clkbuf_16 clkbuf_1_0__f_serial_clock (.A(clknet_0_serial_clock),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.X(clknet_1_0__leaf_serial_clock));
|
|
sky130_fd_sc_hd__clkbuf_16 clkbuf_1_0__f_serial_load (.A(clknet_0_serial_load),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.X(clknet_1_0__leaf_serial_load));
|
|
sky130_fd_sc_hd__clkbuf_16 clkbuf_1_1__f_serial_clock (.A(clknet_0_serial_clock),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.X(clknet_1_1__leaf_serial_clock));
|
|
sky130_fd_sc_hd__clkbuf_16 clkbuf_1_1__f_serial_load (.A(clknet_0_serial_load),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.X(clknet_1_1__leaf_serial_load));
|
|
sky130_fd_sc_hd__conb_1 const_source (.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.HI(one),
|
|
.LO(zero));
|
|
sky130_fd_sc_hd__einvp_8 gpio_in_buf (.A(_001_),
|
|
.TE(gpio_logic1),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.Z(user_gpio_in));
|
|
gpio_logic_high gpio_logic_high (.gpio_logic1(gpio_logic1),
|
|
.vccd1(vccd1),
|
|
.vssd1(vssd1));
|
|
sky130_fd_sc_hd__dlygate4sd3_1 hold1 (.A(\shift_register[12] ),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.X(net15));
|
|
sky130_fd_sc_hd__dlygate4sd3_1 hold10 (.A(\shift_register[6] ),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.X(net24));
|
|
sky130_fd_sc_hd__dlygate4sd3_1 hold11 (.A(\shift_register[7] ),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.X(net25));
|
|
sky130_fd_sc_hd__dlygate4sd3_1 hold12 (.A(\shift_register[5] ),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.X(net26));
|
|
sky130_fd_sc_hd__dlygate4sd3_1 hold13 (.A(\shift_register[11] ),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.X(net27));
|
|
sky130_fd_sc_hd__dlygate4sd3_1 hold2 (.A(\shift_register[9] ),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.X(net16));
|
|
sky130_fd_sc_hd__dlygate4sd3_1 hold3 (.A(\shift_register[2] ),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.X(net17));
|
|
sky130_fd_sc_hd__dlygate4sd3_1 hold4 (.A(\shift_register[3] ),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.X(net18));
|
|
sky130_fd_sc_hd__dlygate4sd3_1 hold5 (.A(\shift_register[1] ),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.X(net19));
|
|
sky130_fd_sc_hd__dlygate4sd3_1 hold6 (.A(\shift_register[0] ),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.X(net20));
|
|
sky130_fd_sc_hd__dlygate4sd3_1 hold7 (.A(\shift_register[8] ),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.X(net21));
|
|
sky130_fd_sc_hd__dlygate4sd3_1 hold8 (.A(\shift_register[10] ),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.X(net22));
|
|
sky130_fd_sc_hd__dlygate4sd3_1 hold9 (.A(\shift_register[4] ),
|
|
.VGND(vssd),
|
|
.VNB(vssd),
|
|
.VPB(vccd),
|
|
.VPWR(vccd),
|
|
.X(net23));
|
|
endmodule
|