caravel/verilog
kareem ac1928a45b harden: gpio_control_block with updated rtl
TODO: run full verification
2022-08-15 02:29:01 -07:00
..
dv Introduction of PDK variable (#39) 2022-04-08 09:05:58 -07:00
gl harden: gpio_control_block with updated rtl 2022-08-15 02:29:01 -07:00
rtl Modified the GPIO control block verilog to remove the delay stages 2022-07-24 16:17:56 -04:00
stubs [DATA] Add spare_logic_block 2021-11-24 20:36:23 +02:00