caravel/verilog
M0stafaRady b31efbdeea IO[0] affects the uart selecting btw system and debug 2022-10-05 13:47:23 -07:00
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dv IO[0] affects the uart selecting btw system and debug 2022-10-05 13:47:23 -07:00
gl Merge pull request #137 from efabless/fix_caravan_gpio_default 2022-10-04 19:03:46 +02:00
rtl Merge branch 'caravel_redesign' into cocotb 2022-10-05 08:24:30 -07:00
stubs [DATA] Add spare_logic_block 2021-11-24 20:36:23 +02:00