Tim Edwards b23ec956f3 Corrected the mprj_bitbang testbench verilog (it had not been corrected for ... the change in the implementation of the serial loader, which split the load signal out as a separate bit, and therefore had a separate bit-bang entry).		2021-12-03 15:06:15 -05:00
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dv	Corrected the mprj_bitbang testbench verilog (it had not been corrected for	2021-12-03 15:06:15 -05:00
gl	[DATA] Update caravel_clocking	2021-12-02 22:50:20 +02:00
rtl	Changed the synchronized reset to occur on the clock falling edge	2021-12-02 14:26:59 -05:00
stubs	[DATA] Add spare_logic_block	2021-11-24 20:36:23 +02:00