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Tim Edwards b23ec956f3 Corrected the mprj_bitbang testbench verilog (it had not been corrected for the change in the implementation of the serial loader, which split the load signal out as a separate bit, and therefore had a separate bit-bang entry).		2021-12-03 15:06:15 -05:00
def	[DATA] Update caravel_clocking	2021-12-02 22:50:20 +02:00
doc	Updated the floorplan.	2021-11-10 12:21:22 -05:00
gds	[DATA] Update caravel_clocking	2021-12-02 22:50:20 +02:00
lef	[DATA] Update caravel_clocking	2021-12-02 22:50:20 +02:00
mag	Reworked part of the layouts of both caravel and caravan to move	2021-12-02 20:45:39 -05:00
maglef	[DATA] Update caravel_clocking	2021-12-02 22:50:20 +02:00
openlane	[DATA] Update caravel_clocking	2021-12-02 22:50:20 +02:00
scripts	Extended the gen_gpio_defaults.py script to handle modifying the	2021-12-02 16:04:51 -05:00
sdc	[DATA] Update caravel_clocking	2021-12-02 22:50:20 +02:00
sdf	[DATA] Update caravel_clocking	2021-12-02 22:50:20 +02:00
signoff	[DATA] Update caravel_clocking	2021-12-02 22:50:20 +02:00
spef	[DATA] Update caravel_clocking	2021-12-02 22:50:20 +02:00
spi/lvs	[DATA] Update caravel_clocking	2021-12-02 22:50:20 +02:00
verilog	Corrected the mprj_bitbang testbench verilog (it had not been corrected for	2021-12-03 15:06:15 -05:00
xschem	Added the files for the simple_por block design, and placed the latest	2021-11-15 10:34:52 -05:00
.gitignore	added install_mcw make target	2021-11-24 09:23:58 -08:00
Makefile	Merge branch 'main' of https://github.com/efabless/caravel_openframe into main	2021-12-02 21:20:59 +02:00
README.md	Update README.md	2021-10-12 10:28:29 -07:00
info.yaml	Modified the set_user_id script so that if it happens to be run on	2021-11-15 16:41:04 -05:00

README.md

caravel_openframe

This is an ongoing investigation regarding the creation of a new openframe based version of Caravel.

Link to schedule: https://plan.tomsplanner.com/public/caravel-openframe