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Tim Edwards a7fec91c4c Update to the back-door wishbone access to housekeeping to better 
implement the arbitration between SPI and back-door.  The back-door
access flags when it is going to do a read or write, and the SPI
can have an invalid read or fail a write if the SPI is too fast,
but the wishbone access should be valid.  As long as the SPI is
much slower than the core clock (say, 1MHz) then there should be no
contention, which means that contention can always be avoided simply
by slowing the SPI signaling down.
 		2021-10-24 16:58:47 -04:00
doc Added block diagrams for documentation. 2021-10-22 12:01:08 -04:00
verilog Update to the back-door wishbone access to housekeeping to better 2021-10-24 16:58:47 -04:00
README.md Update README.md 2021-10-12 10:28:29 -07:00

README.md

caravel_openframe

This is an ongoing investigation regarding the creation of a new openframe based version of Caravel.

Link to schedule: https://plan.tomsplanner.com/public/caravel-openframe