Tim Edwards a7fec91c4c Update to the back-door wishbone access to housekeeping to better ... implement the arbitration between SPI and back-door. The back-door access flags when it is going to do a read or write, and the SPI can have an invalid read or fail a write if the SPI is too fast, but the wishbone access should be valid. As long as the SPI is much slower than the core clock (say, 1MHz) then there should be no contention, which means that contention can always be avoided simply by slowing the SPI signaling down.		2021-10-24 16:58:47 -04:00
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dv/caravel	Corrected the last testbenches, added a new testbench for the spi_master	2021-10-21 19:48:24 -04:00
rtl	Update to the back-door wishbone access to housekeeping to better	2021-10-24 16:58:47 -04:00