mirror of https://github.com/efabless/caravel.git
126 lines
4.3 KiB
Python
126 lines
4.3 KiB
Python
from curses import baudrate
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import random
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import cocotb
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from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles,Timer
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import cocotb.log
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from cpu import RiskV
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from defsParser import Regs
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from cocotb.result import TestSuccess
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from tests.common_functions.test_functions import *
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from tests.bitbang.bitbang_functions import *
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from caravel import GPIO_MODE
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bit_time_ns = 0
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reg = Regs()
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@cocotb.test()
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@repot_test
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async def uart_tx(dut):
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caravelEnv,clock = await test_configure(dut,timeout_cycles=375862)
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cpu = RiskV(dut)
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cpu.cpu_force_reset()
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cpu.cpu_release_reset()
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cocotb.log.info(f"[TEST] Start uart test")
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expected_msg = "Monitor: Test UART (RTL) passed"
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# calculate bit time
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clk = clock.period/1000
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global bit_time_ns
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bit_time_ns = round(10**5 * clk / (96))
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# wait for start of sending
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await wait_reg1(cpu,caravelEnv,0XAA)
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cocotb.log.info (f"[TEST] start receiving from uart")
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counter =0
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data_out =''
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while True:
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if counter %8 == 0:
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if counter != 0:
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data_out = data_out+chr(int(char,2))
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cocotb.log.info (f"[TEST] msg is:'{data_out}' expected '{expected_msg}'")
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if data_out == expected_msg:
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cocotb.log.info (f"[TEST] Pass recieve the full expected msg '{data_out}'")
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break
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await start_of_tx(caravelEnv)
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char = ''
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# if temp != caravelEnv.monitor_gpio((6,6))
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char = caravelEnv.monitor_gpio((6,6)).binstr + char
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cocotb.log.debug (f"[TEST] bit[{counter}] = {caravelEnv.monitor_gpio((6,6))} data out = {char} ")
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await Timer(bit_time_ns, units='ns')
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counter +=1
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async def start_of_tx(caravelEnv):
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while (True): # wait for the start of the transimission it 1 then 0
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if (caravelEnv.monitor_gpio((6,6)).integer == 0):
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break
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await Timer(bit_time_ns, units='ns')
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await Timer(bit_time_ns, units='ns')
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@cocotb.test()
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@repot_test
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async def uart_rx(dut):
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caravelEnv,clock = await test_configure(dut,timeout_cycles=95844)
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cpu = RiskV(dut)
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cpu.cpu_force_reset()
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cpu.cpu_release_reset()
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cocotb.log.info(f"[TEST] Start uart test")
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caravelEnv.drive_gpio_in((0,0),0) # IO[0] affects the uart selecting btw system and debug
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caravelEnv.drive_gpio_in((5,5),1)
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# calculate bit time
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clk = clock.period/1000
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global bit_time_ns
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bit_time_ns = round(10**5 * clk / (96))
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print (clk)
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# send first char
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await wait_reg1(cpu,caravelEnv,0XAA)
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await uart_send_char(caravelEnv,"B")
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await uart_check_char_recieved(caravelEnv,cpu)
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# send second char
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await wait_reg1(cpu,caravelEnv,0XBB)
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await uart_send_char(caravelEnv,"M")
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await uart_check_char_recieved(caravelEnv,cpu)
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# send third char
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await wait_reg1(cpu,caravelEnv,0XCC)
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await uart_send_char(caravelEnv,"A")
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await uart_check_char_recieved(caravelEnv,cpu)
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async def uart_send_char(caravelEnv,char):
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char_bits = [int(x) for x in '{:08b}'.format(ord(char))]
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cocotb.log.info (f"[TEST] start sending on uart {char}")
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#send start bit
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caravelEnv.drive_gpio_in((5,5),0)
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await Timer(bit_time_ns, units='ns')
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#send bits
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for i in range(8):
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caravelEnv.drive_gpio_in((5,5),char_bits[i])
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await Timer(bit_time_ns, units='ns')
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# stop of frame
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caravelEnv.drive_gpio_in((5,5),1)
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await Timer(bit_time_ns, units='ns')
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await Timer(bit_time_ns, units='ns')
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# insert 4 bit delay just for debugging
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await Timer(bit_time_ns, units='ns')
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await Timer(bit_time_ns, units='ns')
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await Timer(bit_time_ns, units='ns')
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await Timer(bit_time_ns, units='ns')
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async def uart_check_char_recieved(caravelEnv,cpu):
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# check cpu recieved the correct character
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while True:
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reg_uart_data = caravelEnv.caravel_hdl.soc.core.uart_rxtx_w.value.binstr
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reg1 = cpu.read_debug_reg1()
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cocotb.log.debug(f"[TEST] reg1 = {hex(reg1)}")
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if reg1 == 0x1B:
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cocotb.log.info(f"[TEST] Pass cpu has recieved the correct character {chr(int(reg_uart_data,2))}")
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return
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if reg1 == 0x1E:
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cocotb.log.error(f"[TEST] Failed Pass cpu has recieved the wrong character {chr(int(reg_uart_data,2))}")
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return
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await ClockCycles(caravelEnv.clk,1) |