mirror of https://github.com/efabless/caravel.git
62 lines
1.7 KiB
Verilog
62 lines
1.7 KiB
Verilog
// SPDX-FileCopyrightText: 2020 Efabless Corporation
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// SPDX-License-Identifier: Apache-2.0
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/* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
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module mgmt_protect_hv(mprj2_vdd_logic1, mprj_vdd_logic1, vccd, vssd, vdda1, vssa1, vdda2, vssa2);
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output mprj2_vdd_logic1;
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wire mprj2_vdd_logic1_h;
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output mprj_vdd_logic1;
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wire mprj_vdd_logic1_h;
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input vccd;
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input vdda1;
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input vdda2;
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input vssa2;
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input vssa1;
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input vssd;
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sky130_fd_sc_hvl__conb_1 mprj2_logic_high_hvl (
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.HI(mprj2_vdd_logic1_h),
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vdda2),
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.VPWR(vdda2)
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);
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sky130_fd_sc_hvl__lsbufhv2lv_1 mprj2_logic_high_lv (
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.A(mprj2_vdd_logic1_h),
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.LVPWR(vccd),
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vdda2),
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.VPWR(vdda2),
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.X(mprj2_vdd_logic1)
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);
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sky130_fd_sc_hvl__conb_1 mprj_logic_high_hvl (
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.HI(mprj_vdd_logic1_h),
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vdda1),
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.VPWR(vdda1)
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);
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sky130_fd_sc_hvl__lsbufhv2lv_1 mprj_logic_high_lv (
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.A(mprj_vdd_logic1_h),
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.LVPWR(vccd),
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.VGND(vssd),
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.VNB(vssd),
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.VPB(vdda1),
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.VPWR(vdda1),
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.X(mprj_vdd_logic1)
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);
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assign vssd = vssa2;
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assign vssa1 = vssa2;
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endmodule |