History

Tim Edwards 7a45a096a5 Added a testbench that exercises the SRAM 2nd (read-only) port, as it was configured for the caravel_pico SoC, with the housekeeping SPI able to access the upper 256-word section of the memory if the CSB bit in the housekeeping control register is cleared. This testbench tests both access through housekeeping and access directly from the SoC through the memory-mapped address.		2021-12-29 11:24:17 -05:00
..
caravel	Added a testbench that exercises the SRAM 2nd (read-only) port, as	2021-12-29 11:24:17 -05:00
wb_utests	Corrected the two failing testbenches (which needed fixing because	2021-10-28 22:20:46 -04:00
README.md	adding user_project_wrapper empty files -- gds & lef	2021-12-16 12:29:35 -08:00
dummy_slave.v	adding user_project_wrapper empty files -- gds & lef	2021-12-16 12:29:35 -08:00

DV Tests

Organized into two subdirectories:

caravel: contains tests for both the mangement SoC and an example user project.
wb_utests: contains unit tests for the wishbone components residing at the management SoC private bus

├── caravel
│   ├── mgmt_soc
│   ├── user_proj_example
└── wb_utests