Tim Edwards 7a45a096a5 Added a testbench that exercises the SRAM 2nd (read-only) port, as ... it was configured for the caravel_pico SoC, with the housekeeping SPI able to access the upper 256-word section of the memory if the CSB bit in the housekeeping control register is cleared. This testbench tests both access through housekeeping and access directly from the SoC through the memory-mapped address.		2021-12-29 11:24:17 -05:00
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dv	Added a testbench that exercises the SRAM 2nd (read-only) port, as	2021-12-29 11:24:17 -05:00
gl	[DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells	2021-12-24 21:06:58 +02:00
rtl	Added a reference to the new file "gl/mgmt_defines.v" in the	2021-12-24 11:46:34 -05:00
stubs	[DATA] Add spare_logic_block	2021-11-24 20:36:23 +02:00