| .. |
|
__uprj_analog_netlists.v
|
Seeding with documentation of pinout and verilog RTL (mostly unchanged
|
2021-10-12 16:31:42 -04:00 |
|
__uprj_netlists.v
|
Seeding with documentation of pinout and verilog RTL (mostly unchanged
|
2021-10-12 16:31:42 -04:00 |
|
__user_analog_project_wrapper.v
|
Seeding with documentation of pinout and verilog RTL (mostly unchanged
|
2021-10-12 16:31:42 -04:00 |
|
__user_project_wrapper.v
|
Add RTL for 2 debug regs used to test and located inside user_project_wrapper
|
2022-09-30 03:52:34 -07:00 |
|
caravan.v
|
152 add pass thru for clock and reset (#154)
|
2022-10-07 01:36:26 -07:00 |
|
caravan_netlists.v
|
Merge branch 'caravel_redesign' into make_CSB_a_pullup
|
2022-10-06 11:39:22 -04:00 |
|
caravan_openframe.v
|
Renamed the poorly and awkwardly named "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped"
|
2021-10-31 21:43:09 -04:00 |
|
caravel.v
|
152 add pass thru for clock and reset (#154)
|
2022-10-07 01:36:26 -07:00 |
|
caravel_clocking.v
|
Changed the synchronized reset to occur on the clock falling edge
|
2021-12-02 14:26:59 -05:00 |
|
caravel_netlists.v
|
Merge branch 'caravel_redesign' into make_CSB_a_pullup
|
2022-10-06 11:39:22 -04:00 |
|
caravel_openframe.v
|
Renamed the poorly and awkwardly named "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped"
|
2021-10-31 21:43:09 -04:00 |
|
chip_io.v
|
Flipped some lines where a wire was used before it was declared.
|
2022-09-20 18:23:32 -04:00 |
|
chip_io_alt.v
|
Modified the GPIO control block to buffer the constant high/low outputs.
|
2022-09-20 17:49:08 -04:00 |
|
clock_div.v
|
Fixed one bad error in clock_div which had been done without my
|
2021-12-06 21:37:51 -05:00 |
|
constant_block.v
|
Modified the GPIO control block to buffer the constant high/low outputs.
|
2022-09-20 17:49:08 -04:00 |
|
debug_regs.v
|
fix bug at reading from debug registers
|
2022-10-03 08:57:23 -07:00 |
|
defines.v
|
Update storage testbench to work with one 2K block
|
2021-11-12 17:14:21 +02:00 |
|
digital_pll.v
|
fixes for RTL testbenches with mgmt core wrapper
|
2021-12-05 10:11:10 -08:00 |
|
digital_pll_controller.v
|
Seeding with documentation of pinout and verilog RTL (mostly unchanged
|
2021-10-12 16:31:42 -04:00 |
|
gpio_control_block.v
|
Merge branch 'caravel_redesign' into fix_direct_power_connections
|
2022-10-05 21:33:17 -04:00 |
|
gpio_defaults_block.v
|
Implemented a system for setting the GPIO power-on defaults through
|
2021-10-23 17:18:30 -04:00 |
|
gpio_logic_high.v
|
Seeding with documentation of pinout and verilog RTL (mostly unchanged
|
2021-10-12 16:31:42 -04:00 |
|
housekeeping.v
|
merge caravel_redesign
|
2022-10-07 06:06:14 -07:00 |
|
housekeeping_spi.v
|
Modified the housekeeping SPI to generate a read strobe (or rather
|
2021-10-23 22:06:24 -04:00 |
|
mgmt_protect.v
|
fix some typos on mgmt_protect
|
2022-10-05 03:27:46 -07:00 |
|
mgmt_protect_hv.v
|
Seeding with documentation of pinout and verilog RTL (mostly unchanged
|
2021-10-12 16:31:42 -04:00 |
|
mprj2_logic_high.v
|
Seeding with documentation of pinout and verilog RTL (mostly unchanged
|
2021-10-12 16:31:42 -04:00 |
|
mprj_io.v
|
Corrections to the padframe to make sure that all pad digital
|
2022-09-20 16:00:09 -04:00 |
|
mprj_logic_high.v
|
Revised the management protect block to include protections against
|
2021-10-27 19:36:43 -04:00 |
|
pads.v
|
Modified the GPIO control block to buffer the constant high/low outputs.
|
2022-09-20 17:49:08 -04:00 |
|
ring_osc2x13.v
|
Seeding with documentation of pinout and verilog RTL (mostly unchanged
|
2021-10-12 16:31:42 -04:00 |
|
simple_por.v
|
Modified simple_por.v RTL to avoid the wire declaration that "cvc"
|
2021-12-08 12:16:19 -05:00 |
|
spare_logic_block.v
|
Revised the spare logic block to make sure that all inputs are
|
2021-11-24 09:34:52 -05:00 |
|
user_defines.v
|
Split the layout of the GPIO defaults block into three versions, for the
|
2021-11-06 13:28:26 -04:00 |
|
user_id_programming.v
|
Implemented a system for setting the GPIO power-on defaults through
|
2021-10-23 17:18:30 -04:00 |
|
xres_buf.v
|
Renamed the poorly and awkwardly named "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped"
|
2021-10-31 21:43:09 -04:00 |
6f832589c0