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Tim Edwards 624317bc3f Corrected the missing port designation on porb_h in chip_io.mag
and chip_io_alt.mag.
2021-12-07 12:38:18 -05:00
def [DATA] Update caravel_clocking 2021-12-07 13:36:56 +02:00
doc Updated the floorplan. 2021-11-10 12:21:22 -05:00
gds [DATA] Update GDS views for the chip_io/chip_io_alt/mgmt_protect_hv/mgmt_protect to match the mag view 2021-12-07 14:28:29 +02:00
lef [DATA] Update caravel_clocking 2021-12-07 13:36:56 +02:00
mag Corrected the missing port designation on porb_h in chip_io.mag 2021-12-07 12:38:18 -05:00
maglef [DATA] Update caravel_clocking 2021-12-07 13:36:56 +02:00
openlane [DATA] Update caravel_clocking 2021-12-07 13:36:56 +02:00
scripts Correction to the gen_gpio_defaults.py file, which was accidentally 2021-12-04 12:41:06 -05:00
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spi/lvs [DATA] Update caravel_clocking 2021-12-07 13:36:56 +02:00
verilog Corrected an error in verilog/gl/chip_io_alt.v, which was missing 2021-12-07 10:06:35 -05:00
xschem Added the files for the simple_por block design, and placed the latest 2021-11-15 10:34:52 -05:00
.gitignore added install_mcw make target 2021-11-24 09:23:58 -08:00
Makefile Merge branch 'main' of https://github.com/efabless/caravel_openframe into main 2021-12-07 13:01:52 +02:00
README.md Update README.md 2021-10-12 10:28:29 -07:00
info.yaml Modified the set_user_id script so that if it happens to be run on 2021-11-15 16:41:04 -05:00

README.md

caravel_openframe

This is an ongoing investigation regarding the creation of a new openframe based version of Caravel.

Link to schedule: https://plan.tomsplanner.com/public/caravel-openframe