mirror of https://github.com/efabless/caravel.git
89 lines
3.6 KiB
Python
89 lines
3.6 KiB
Python
import random
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import cocotb
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from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
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import cocotb.log
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from cpu import RiskV
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from defsParser import Regs
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from cocotb.result import TestSuccess
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from tests.common_functions.test_functions import *
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from tests.bitbang.bitbang_functions import *
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from caravel import GPIO_MODE
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from cocotb.binary import BinaryValue
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from tests.housekeeping.housekeeping_spi.spi_access_functions import *
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reg = Regs()
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caravel_clock = 0
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user_clock = 0
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core_clock = 0
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@cocotb.test()
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@repot_test
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async def clock_redirect(dut):
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caravelEnv,clock = await test_configure(dut,timeout_cycles=264012)
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cpu = RiskV(dut)
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cpu.cpu_force_reset()
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cpu.cpu_release_reset()
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# calculate core clock
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await cocotb.start(calculate_clk_period(dut.uut.clock,"core clock"))
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await ClockCycles(caravelEnv.clk,110)
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cocotb.log.info(f"[TEST] core clock requency = {round(1000000/core_clock,2)} MHz period = {core_clock}ps")
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await wait_reg1(cpu,caravelEnv,0xAa)
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# check clk redirect working
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#user clock
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clock_name = "user clock"
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await write_reg_spi(caravelEnv,0x1b,0x0) # disable user clock output redirect
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await cocotb.start(calculate_clk_period(dut.bin14_monitor,clock_name))
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await ClockCycles(caravelEnv.clk,110)
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if user_clock != 0:
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cocotb.log.error(f"[TEST] Error: {clock_name} is directed while clk2_output_dest is disabled")
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else:
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cocotb.log.info(f"[TEST] Pass: {clock_name} has not directed when reg clk2_output_dest is disabled")
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await write_reg_spi(caravelEnv,0x1b,0x4) # enable user clock output redirect
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await cocotb.start(calculate_clk_period(dut.bin14_monitor,clock_name))
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await ClockCycles(caravelEnv.clk,110)
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if user_clock != core_clock:
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cocotb.log.error(f"[TEST] Error: {clock_name} is directed with wrong value {clock_name} period = {user_clock} and core clock = {core_clock}")
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else:
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cocotb.log.info(f"[TEST] Pass: {clock_name} has directed successfully")
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#caravel clock
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clock_name = "caravel clock"
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await write_reg_spi(caravelEnv,0x1b,0x0) # disable caravel clock output redirect
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await cocotb.start(calculate_clk_period(dut.bin14_monitor,clock_name))
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await ClockCycles(caravelEnv.clk,110)
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if caravel_clock != 0:
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cocotb.log.error(f"[TEST] Error: {clock_name} is directed while clk2_output_dest is disabled")
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else:
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cocotb.log.info(f"[TEST] Pass: {clock_name} has not directed when reg clk2_output_dest is disabled")
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await write_reg_spi(caravelEnv,0x1b,0x4) # enable caravel clock output redirect
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await cocotb.start(calculate_clk_period(dut.bin15_monitor,clock_name))
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await ClockCycles(caravelEnv.clk,110)
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if caravel_clock != core_clock:
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cocotb.log.error(f"[TEST] Error: {clock_name} is directed with wrong value {clock_name} period = {caravel_clock} and core clock = {core_clock}")
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else:
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cocotb.log.info(f"[TEST] Pass: {clock_name} has directed successfully")
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async def calculate_clk_period(clk,name):
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await RisingEdge(clk)
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initial_time = cocotb.simulator.get_sim_time()
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initial_time = (initial_time[0] <<32) | (initial_time[1])
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for i in range(100):
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await RisingEdge(clk)
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end_time = cocotb.simulator.get_sim_time()
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end_time = (end_time[0] <<32) | (end_time[1])
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val = (end_time - initial_time) / 100
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cocotb.log.debug(f"[TEST] clock of {name} is {val}")
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if name == "caravel clock":
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global caravel_clock
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caravel_clock = val
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elif name == "user clock":
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global user_clock
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user_clock = val
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elif name == "core clock":
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global core_clock
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core_clock = val
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return val
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