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riscv
/
caravel
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https://github.com/efabless/caravel.git
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0be31a26c1
caravel
/
verilog
/
dv
/
cocotb
/
tests
/
uart
History
M0stafaRady
ceac6defa1
fix some tests for gatelevel
2022-10-13 04:05:12 -07:00
..
uart.py
fix some tests for gatelevel
2022-10-13 04:05:12 -07:00
uart_loopback.c
Add test uart_loopback
2022-10-06 03:12:44 -07:00
uart_rx.c
fix uart_rx tests by sending in reverse and use uart_ev_pending_write(UART_EV_RX);
2022-10-06 02:14:59 -07:00
uart_tx.c
Adding cocotb evironment with tests and scripts to run
2022-09-30 03:52:34 -07:00