mirror of https://github.com/efabless/caravel.git
212 lines
9.6 KiB
Plaintext
212 lines
9.6 KiB
Plaintext
Metric,Value
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timing__setup__ws__corner:nom_tt_025C_1v80,1.624232
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timing__hold__ws__corner:nom_tt_025C_1v80,0.274621
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design__instance__area,3221.84
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design__instance__count,520
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design__instance__total_power,1.3465
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design__die__bbox,0.0 0.0 100.0 75.0
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design__core__bbox,5.52 5.44 94.3 68.0
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design__io,39
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design__die__area,7500
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design__core__area,5554.08
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design__instance__count__stdcell,520
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design__instance__area__stdcell,3221.84
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design__instance__count__macros,0
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design__instance__area__macros,0
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design__instance__utilization,0.580086
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design__instance__utilization__stdcell,0.580086
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design__instance__count__setup_buffer,0
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design__instance__count__hold_buffer,0
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design__instance__displacement__total,0
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design__instance__displacement__mean,0
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design__instance__displacement__max,0
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route__wirelength__estimated,6909.71
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design__violations,0
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antenna__violating__nets,0
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antenna__violating__pins,0
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antenna__count,0
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route__net,394
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route__net__special,2
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route__drc_errors__iter:1,168
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route__wirelength__iter:1,7682
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route__drc_errors__iter:2,55
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route__wirelength__iter:2,7648
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route__drc_errors__iter:3,123
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route__wirelength__iter:3,7652
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route__drc_errors__iter:4,1
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route__wirelength__iter:4,7689
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route__drc_errors__iter:5,0
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route__wirelength__iter:5,7689
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route__drc_errors,0
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route__wirelength,7689
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route__vias,2382
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route__vias__singlecut,2382
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route__vias__multicut,0
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design__disconnected_pins__count,0
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route__wirelength__max,252.91
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design__max_slew_violation__count__corner:nom_tt_025C_1v80,0
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design__max_fanout_violation__count__corner:nom_tt_025C_1v80,2
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design__max_cap_violation__count__corner:nom_tt_025C_1v80,0
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power__internal__total,0.0006281010573729873
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power__switching__total,0.0010574385523796082
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power__leakage__total,3.840616269457087e-09
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power__total,0.0016855434514582157
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clock__skew__worst_hold__corner:nom_tt_025C_1v80,-0.026419
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clock__skew__worst_setup__corner:nom_tt_025C_1v80,0.026648
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timing__hold__tns__corner:nom_tt_025C_1v80,0.0
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timing__setup__tns__corner:nom_tt_025C_1v80,0.0
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timing__hold__wns__corner:nom_tt_025C_1v80,0.0
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timing__setup__wns__corner:nom_tt_025C_1v80,0.0
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timing__hold_vio__count__corner:nom_tt_025C_1v80,0
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timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80,0
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timing__setup_vio__count__corner:nom_tt_025C_1v80,0
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timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80,0
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design__max_slew_violation__count__corner:nom_ss_100C_1v60,0
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design__max_fanout_violation__count__corner:nom_ss_100C_1v60,2
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design__max_cap_violation__count__corner:nom_ss_100C_1v60,0
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clock__skew__worst_hold__corner:nom_ss_100C_1v60,-0.026351
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clock__skew__worst_setup__corner:nom_ss_100C_1v60,0.026574
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timing__hold__ws__corner:nom_ss_100C_1v60,0.67865
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timing__setup__ws__corner:nom_ss_100C_1v60,-2.045736
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timing__hold__tns__corner:nom_ss_100C_1v60,0.0
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timing__setup__tns__corner:nom_ss_100C_1v60,-9.303928
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timing__hold__wns__corner:nom_ss_100C_1v60,0.0
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timing__setup__wns__corner:nom_ss_100C_1v60,-2.045736
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timing__hold_vio__count__corner:nom_ss_100C_1v60,0
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timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60,0
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timing__setup_vio__count__corner:nom_ss_100C_1v60,8
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timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60,7
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design__max_slew_violation__count__corner:nom_ff_n40C_1v95,0
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design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,2
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design__max_cap_violation__count__corner:nom_ff_n40C_1v95,0
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clock__skew__worst_hold__corner:nom_ff_n40C_1v95,-0.026447
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clock__skew__worst_setup__corner:nom_ff_n40C_1v95,0.026678
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timing__hold__ws__corner:nom_ff_n40C_1v95,0.139551
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timing__setup__ws__corner:nom_ff_n40C_1v95,2.729408
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timing__hold__tns__corner:nom_ff_n40C_1v95,0.0
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timing__setup__tns__corner:nom_ff_n40C_1v95,0.0
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timing__hold__wns__corner:nom_ff_n40C_1v95,0.0
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timing__setup__wns__corner:nom_ff_n40C_1v95,0.0
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timing__hold_vio__count__corner:nom_ff_n40C_1v95,0
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timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95,0
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timing__setup_vio__count__corner:nom_ff_n40C_1v95,0
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timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95,0
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design__max_slew_violation__count__corner:min_tt_025C_1v80,0
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design__max_fanout_violation__count__corner:min_tt_025C_1v80,2
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design__max_cap_violation__count__corner:min_tt_025C_1v80,0
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clock__skew__worst_hold__corner:min_tt_025C_1v80,-0.019092
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clock__skew__worst_setup__corner:min_tt_025C_1v80,0.019238
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timing__hold__ws__corner:min_tt_025C_1v80,0.274164
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timing__setup__ws__corner:min_tt_025C_1v80,1.663321
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timing__hold__tns__corner:min_tt_025C_1v80,0.0
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timing__setup__tns__corner:min_tt_025C_1v80,0.0
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timing__hold__wns__corner:min_tt_025C_1v80,0.0
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timing__setup__wns__corner:min_tt_025C_1v80,0.0
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timing__hold_vio__count__corner:min_tt_025C_1v80,0
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timing__hold_r2r_vio__count__corner:min_tt_025C_1v80,0
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timing__setup_vio__count__corner:min_tt_025C_1v80,0
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timing__setup_r2r_vio__count__corner:min_tt_025C_1v80,0
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design__max_slew_violation__count__corner:min_ss_100C_1v60,0
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design__max_fanout_violation__count__corner:min_ss_100C_1v60,2
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design__max_cap_violation__count__corner:min_ss_100C_1v60,0
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clock__skew__worst_hold__corner:min_ss_100C_1v60,-0.018972
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clock__skew__worst_setup__corner:min_ss_100C_1v60,0.019113
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timing__hold__ws__corner:min_ss_100C_1v60,0.67585
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timing__setup__ws__corner:min_ss_100C_1v60,-1.833309
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timing__hold__tns__corner:min_ss_100C_1v60,0.0
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timing__setup__tns__corner:min_ss_100C_1v60,-8.749656
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timing__hold__wns__corner:min_ss_100C_1v60,0.0
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timing__setup__wns__corner:min_ss_100C_1v60,-1.833309
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timing__hold_vio__count__corner:min_ss_100C_1v60,0
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timing__hold_r2r_vio__count__corner:min_ss_100C_1v60,0
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timing__setup_vio__count__corner:min_ss_100C_1v60,8
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timing__setup_r2r_vio__count__corner:min_ss_100C_1v60,7
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design__max_slew_violation__count__corner:min_ff_n40C_1v95,0
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design__max_fanout_violation__count__corner:min_ff_n40C_1v95,2
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design__max_cap_violation__count__corner:min_ff_n40C_1v95,0
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clock__skew__worst_hold__corner:min_ff_n40C_1v95,-0.01919
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clock__skew__worst_setup__corner:min_ff_n40C_1v95,0.019339
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timing__hold__ws__corner:min_ff_n40C_1v95,0.139087
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timing__setup__ws__corner:min_ff_n40C_1v95,2.757252
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timing__hold__tns__corner:min_ff_n40C_1v95,0.0
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timing__setup__tns__corner:min_ff_n40C_1v95,0.0
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timing__hold__wns__corner:min_ff_n40C_1v95,0.0
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timing__setup__wns__corner:min_ff_n40C_1v95,0.0
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timing__hold_vio__count__corner:min_ff_n40C_1v95,0
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timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95,0
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timing__setup_vio__count__corner:min_ff_n40C_1v95,0
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timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95,0
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design__max_slew_violation__count__corner:max_tt_025C_1v80,0
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design__max_fanout_violation__count__corner:max_tt_025C_1v80,2
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design__max_cap_violation__count__corner:max_tt_025C_1v80,0
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clock__skew__worst_hold__corner:max_tt_025C_1v80,-0.04563
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clock__skew__worst_setup__corner:max_tt_025C_1v80,0.04611
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timing__hold__ws__corner:max_tt_025C_1v80,0.273634
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timing__setup__ws__corner:max_tt_025C_1v80,1.585729
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timing__hold__tns__corner:max_tt_025C_1v80,0.0
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timing__setup__tns__corner:max_tt_025C_1v80,0.0
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timing__hold__wns__corner:max_tt_025C_1v80,0.0
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timing__setup__wns__corner:max_tt_025C_1v80,0.0
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timing__hold_vio__count__corner:max_tt_025C_1v80,0
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timing__hold_r2r_vio__count__corner:max_tt_025C_1v80,0
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timing__setup_vio__count__corner:max_tt_025C_1v80,0
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timing__setup_r2r_vio__count__corner:max_tt_025C_1v80,0
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design__max_slew_violation__count__corner:max_ss_100C_1v60,0
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design__max_fanout_violation__count__corner:max_ss_100C_1v60,2
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design__max_cap_violation__count__corner:max_ss_100C_1v60,0
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clock__skew__worst_hold__corner:max_ss_100C_1v60,-0.046207
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clock__skew__worst_setup__corner:max_ss_100C_1v60,0.046689
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timing__hold__ws__corner:max_ss_100C_1v60,0.680917
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timing__setup__ws__corner:max_ss_100C_1v60,-2.245377
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timing__hold__tns__corner:max_ss_100C_1v60,0.0
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timing__setup__tns__corner:max_ss_100C_1v60,-9.948954
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timing__hold__wns__corner:max_ss_100C_1v60,0.0
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timing__setup__wns__corner:max_ss_100C_1v60,-2.245377
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timing__hold_vio__count__corner:max_ss_100C_1v60,0
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timing__hold_r2r_vio__count__corner:max_ss_100C_1v60,0
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timing__setup_vio__count__corner:max_ss_100C_1v60,8
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timing__setup_r2r_vio__count__corner:max_ss_100C_1v60,7
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design__max_slew_violation__count__corner:max_ff_n40C_1v95,0
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design__max_fanout_violation__count__corner:max_ff_n40C_1v95,2
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design__max_cap_violation__count__corner:max_ff_n40C_1v95,0
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clock__skew__worst_hold__corner:max_ff_n40C_1v95,-0.044996
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clock__skew__worst_setup__corner:max_ff_n40C_1v95,0.045482
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timing__hold__ws__corner:max_ff_n40C_1v95,0.139449
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timing__setup__ws__corner:max_ff_n40C_1v95,2.701741
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timing__hold__tns__corner:max_ff_n40C_1v95,0.0
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timing__setup__tns__corner:max_ff_n40C_1v95,0.0
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timing__hold__wns__corner:max_ff_n40C_1v95,0.0
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timing__setup__wns__corner:max_ff_n40C_1v95,0.0
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timing__hold_vio__count__corner:max_ff_n40C_1v95,0
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timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95,0
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timing__setup_vio__count__corner:max_ff_n40C_1v95,0
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timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95,0
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design__max_slew_violation__count,0
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design__max_fanout_violation__count,18
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design__max_cap_violation__count,0
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clock__skew__worst_hold,-0.018972
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clock__skew__worst_setup,0.046689
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timing__hold__ws,0.139087
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timing__setup__ws,-2.245377
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timing__hold__tns,0.0
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timing__setup__tns,-28.002538
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timing__hold__wns,0.0
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timing__setup__wns,-2.245377
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timing__hold_vio__count,0
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timing__hold_r2r_vio__count,0
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timing__setup_vio__count,24
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timing__setup_r2r_vio__count,21
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ir__voltage__worst,1.8000000000000000444089209850062616169452667236328125
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ir__drop__avg,0.000890999999999999973444853029747036998742260038852691650390625
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ir__drop__worst,0.00120999999999999992110477631257481334614567458629608154296875
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design__xor_difference__count,0
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magic__drc_error__count,0
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magic__illegal_overlap__count,0
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design__lvs_device_difference__count,0
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design__lvs_net_differences__count,0
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design__lvs_property_fails__count,0
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design__lvs_errors__count,0
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design__lvs_unmatched_devices__count,0
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design__lvs_unmatched_nets__count,0
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design__lvs_unmatched_pins__count,0
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